Abstract: A home wireless router establishes a Wireless Local Area Network (WLAN) and services a plurality of wireless terminals within the WLAN service area including at least one Voice over Internet Protocol (VoIP) wireless terminal. The home wireless router receives a request from the VoIP wireless terminal to establish a VoIP conference call with at least two other VoIP wireless terminals. The home wireless router interacts with the VoIP service accumulator to determine at least one other home wireless router required to service the VoIP conference call, queries the at least one other home wireless router to determine its ability to service the VoIP conference call for at least one serviced VoIP wireless terminal, and receives a response from the at least one other home wireless router. The home wireless router, the at least one other home wireless router, and the VoIP service accumulator then set up and service the VoIP conference call.

Abstract: A system and method for controlling the delivery of power to a powered device in a Power over Ethernet Broad Reach (PoE-BR) application. Cabling power loss in a PoE-BR application is related to the resistance of the cable itself. A PHY can be designed to measure electrical characteristics (e.g., insertion loss, cross talk, length, etc.) of the Ethernet cable to enable determination of the cable resistance. The determined resistance in a broad reach cable can be used in increasing a power budget allocated to a power source equipment port.

Abstract: A method and system for a multi-rate Media Access Control layer (MAC) to Physical layer (PHY) interface is provided. The method to provide a multi-rate Media Access Control layer (MAC) interface comprises receiving a first set of signals, sampling the first set of signals to determine a type of interface to be used to transmit or receive the first set of signals or a subset of the first set of signals, generating a select signal indicating type of interface to be used based on the sampling step and transmitting the first set of signals or a subset of the first set of signals using the interface indicated by the select signal.

Abstract: A data scrambling circuit is provided. The data scrambling circuit includes an integrated circuit having a digital logic device and an interface circuit coupled to the digital logic device. Also included is an external memory coupled to output pins on the interface circuit. The digital logic device communicates patterned data to the interface circuit. The interface circuit then scrambles the patterned data to produce a pseudo random output to be stored within the external memory and unscrambled a pseudo random signal from the external memory to produce unscrambled data to be read by the digital logic device.

Abstract: Quadratic polynomial permutation (QPP) interleaver providing hardware saving and flexible granularity adaptable to any possible turbo code block size. A means is presented by which only a very small number of coefficients need be stored to effectuate a wide variety of QPP interleaves as can be employed in the context of turbo coding. In one instance, to accommodate the approximate 6000 different turbo code block sizes in 3GPP LTE channel coding, only 5 different coefficient values need to be stored to effectuate a very broad range of QPP interleaves to be applied each of those various turbo code block sizes. Moreover, a few small number of dummy bits, if any, need to be employed to accommodate a very broad range of turbo code block sizes. It is noted that the QPP interleaving as described herein can be applied to turbo encoding and turbo decoding (e.g., including both interleaving and de-interleaving).

Abstract: Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave. A means is presented by which any desired number of parallel implemented turbo decoding processors can be employed to perform turbo decoding that has been performed using a QPP interleave. This approach is presented to allow an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) to perform decoding of a turbo coded signal while still using a selected embodiment of a QPP interleave. In addition, a collision-free memory mapping, MOD,C,W) provides more freedom for selecting the particular quadratic polynomial permutation (QPP) interleave (?) that satisfies a parallel turbo decoding implementation with any desired number of parallel implemented turbo decoding processors.

Abstract: A system and method for discovering a cable type using an automated, systematic process. A PHY can be designed to measure electrical characteristics (e.g., insertion loss, cross talk, length, etc.) of the cable to enable determination of the cable type. The determined cable type can be used in diagnosis of cabling infrastructure or in a dynamic configuration or operation process.

Abstract: A method for transmitting wide bandwidth signals in a network that includes legacy devices begins by determining channel bandwidth of a channel that supports the wide bandwidth signals in the network. The method continues by determining overlap of legacy channel bandwidth with the channel bandwidth of the channel. The method continues by providing a legacy readable preamble section within the channel where the legacy channel bandwidth overlaps the channel bandwidth of the channel.

Abstract: Amplifying magnitude metric of received signals during iterative decoding of LDPC code and LDPC coded modulation. By appropriately selecting a metric coefficient value that is used to calculate the initial conditions when decoding LDPC coded signals, a significant reduction in BER may be achieved at certain SNRs. The appropriate selection of the metric coefficient value may be performed depending on the particular SNR at which a communication system is operating. By adjusting this metric coefficient value according to the given LDPC code, modulation, and noise variance, the overall performance of the decoding may be significantly improved. The convergence speed is slowed down so that the decoder will not go to the wrong codeword, and the moving range of the outputs of the decoder is restricted so that the output will not oscillate too much and will eventually move to the correct codeword.

Abstract: A system and method for a generalized packet header suppression mechanism is described. This mechanism is implemented via a descriptor table. An exact copy of the descriptor table is stored in both the sender and receiver of packets via a communication medium. Entries in the descriptor table provide the information necessary to both suppress and expand the headers of well-known packets. The sender of the packet uses the descriptor table to suppress the packet header prior to transmitting the packet over the communication medium. When the packet reaches the receiver, the receiver uses the descriptor table to expand or reconstruct the packet header. This procedure results in less bandwidth required to transmit well-known messages because known header data is not transmitted via the medium, thereby not wasting bandwidth. The suppression mechanism allows the complete suppression of the header of a packet (as opposed to the traditional payload suppression) by a shorter message descriptor.

Abstract: Methods for improving communication performance in a wireless communication system where the wireless communication system has at least one mobile wireless communication device and a plurality of transmitter/receiver sites. The transmitter/receiver sites have a geographic area, defined as a cell, within which the mobile wireless communication devices can communicate with at least one of the transmitter/receiver sites. The methods determine when the mobile wireless communication device should rate shift or roam based on connection quality measurement data or position information such as GPS. In one method, the measurement data is subjected to configurable parameters to create a functional relationship value that is recorded. The recorded functional relationship values are trended and extrapolated to determine whether a rate shift or roam should be performed.

Abstract: According to one exemplary embodiment, an inductor-tuned buffer circuit includes at least one input transistor for receiving a time varying input signal, where the at least one input transistor drives an output of the buffer circuit. The buffer circuit further includes a buffer inductor coupled to the output of the buffer circuit. The buffer circuit is utilized to drive a capacitive load through an interconnecting conductor, where the buffer inductor is situated in proximity to the capacitive load so as to cause a parasitic inductance of the interconnecting conductor to be less than, or much less than, the buffer inductor.

Abstract: According to an example embodiment, an amplitude feedback loop may include an RF amplifier, a detector, a comparator, and a Q-enhancement cell. In an example embodiment, the RF amplifier has an output signal, and the detector has an input coupled to the output signal of the RF amplifier and is configured to detect a level of the output signal of the RF amplifier. The comparator circuit may receive as inputs a reference voltage and the output of the detector. Also, the comparator circuit is configured to output a control signal based on a difference between the reference voltage and the output signal of the power detector. The Q-enhancement cell may be coupled to the RF amplifier and have an input coupled to an output of the comparator circuit. A bias current of the Q-enhancement cell may be adjusted based on the control signal output by the comparator circuit.

Abstract: Methods and apparatus are provided for implementing a cryptography accelerator for performing operations such as hash operations. The cryptography accelerator recognizes characteristics associated with input data and retrieves an instruction set for processing the input data. The instruction set is used to configure or control components such as MD5 and SHA-1 hash cores, XOR components, memory, etc. By providing a cryptography accelerator with access to multiple instruction sets, a variety of hash operations can be performed in a configurable cryptographic accelerator.

Abstract: A counter system and method and computer program product for managing counter systems. Counter systems management includes receiving a count event associated with a counter, updating a first stage counter value based on the count event, determining whether to eject the counter value based on a random function of the counter state, and ejecting the counter value. A counter system comprises a first stage update unit configured to accept a count event and to eject a counter. A second stage update unit may be configured to accept an ejected counter value, and includes a second counting module configured to accumulate the ejected counter value.

Abstract: A system and method of classifying a high powered device (PD) with an increased current limit includes: connecting a voltage to the PD, measuring current through a classification resistor connected to the PD, and determining a PD classification signature based on the current according to classification steps such that a minimum classification step includes a minimum current of 0 mA and a maximum classification step includes a maximum current beyond a predetermined current limit. The system includes a PSE, voltage source, PD classification resistor, and PD voltage, connected to the P. An alternative embodiment further includes a discrete classification circuit and discrete classification resistor to be used to measure the current for classification purposes instead of the PD classification resistor when the PD and PD classification resistor do not support power classification under the classification scheme.

Abstract: Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation. A novel means is presented herein by which error magnitudes (or error values) can be calculated directly without requiring the generation of an error value polynomial (EVP). Modification of the Koetter decoding approach and the Forney formula are employed herein to perform the direct calculation of the error values. This approach is operable to save computation clock cycles that would normally be used to compute the EVP, and these clock cycles may be used to reduce the otherwise required parallelism and complexity in the ECC design that may be needed to perform the error correction in the allotted time and may also result in power savings. Some advantages related to this may approach include lower risk, less design time, and more scalability in an overall design.

Abstract: Area efficient on-the-fly error correction code (ECC) decoder architecture. A novella means is presented by which only 2 banks of registers are employed (as opposed to 3 or more banks) when generating an error location polynomial in accordance with decoding of a Reed-Solomon (RS) coded signal. Berlekamp-Massey decoding processing can be employed when decoding such a RS coded signal. This approach provides for a significant amount of savings in hardware. For example, one embodiment designed in accordance with the invention is operable to implement an entire 12-bit (t=120) Reed-Solomon ECC system for HDD applications which consumes only approximately 170 k gates. Of these 170 k gates, 70K gates are attributed to the syndrome/symbol computer. Moreover, because of the pipelined arrangement of the decoding processing presented herein (which allows for more clock cycles to perform the division), division processing can be performed using an inverter and multiplier.

Abstract: A technique to detect defects when reading a defect scan pattern stored on a disk in which the detected defects are processed differently depending on which region of a sector the defect is resident. In one implementation, a mask is used to identify the defects of different regions. By differentiating different regions within the sector for defect scan, sync mark and preamble fields may be treated as critical regions so that different defect scan properties may be attributed when performing the defect scan.

Abstract: A technique to detect head instability by monitoring for a baseline popping (BLP) noise effect on demodulation bursts read from a disk. In one technique, a digital filter is employed as a moving average filter so that the filtering of the bursts has a zero output from the filter if only the bursts are present. However, when a BLP event occurs, the noise effect causes a non-zero output from the filter. A threshold value is set and when the output of the filter exceeds the threshold value, a BLP indication is noted. Although various filters may be used, in one technique, a filter suitable for use in detecting thermal asperity defects is used for the BLP detection filter.