Abstract: Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its range. One exemplary application is echo cancellation in a full duplex pulse amplitude modulation system with 10 levels (PAM-10). Echo cancellation may be achieved by calculating a digital replica of the echo from the transmission channel. The replica signal may be calculated in a finite impulse response (FIR) filter, which multiplies the transmitted signal with estimates of the echo coefficients of the transmission channel The replica signal may be subtracted from the received signal to create an echo-free receive signal. The disclosed method may reduce the number of partial products between the PAM-10 transmit signal and each echo coefficient from three, when radix-4 Booth coding is used, to two.

Abstract: A direct conversion radio frequency (RF) tuner includes a mixer generating I and Q quadrature components. A phase detection circuit generates a phase error measurement between the I quadrature component and the Q quadrature component. A phase correction circuit corrects a phase of the Q component based on the phase error measurement, and outputs a phase-corrected Q quadrature component. An I quadrature component gain control circuit receives the I quadrature component and outputting an amplitude corrected I quadrature component. A Q quadrature component gain control circuit receives the phase corrected Q quadrature component and outputs an amplitude corrected Q quadrature component.

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can include selectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.

Abstract: According to one general aspect, an apparatus includes a first resistor in a first current path of a resistor-capacitor (RC) circuit, the resistor connected to a power source. A variable capacitor is included in a second current path of the RC circuit and operably connected to the power source and a virtual ground generator. A comparison circuit is configured to make a determination regarding a voltage VR across the resistor to a ground relative to a voltage VC across the capacitor to a virtual ground from the virtual ground generator. A control circuit is configured to make an adjustment of a value of the variable capacitor, based on the determination.

Abstract: The present invention relates to a system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The present invention includes writing a logic 0 into all the memory cells in a memory structure. All the high address predecoded lines and alternating predecoded lines for the lowest address are enabled. A voltage drop between neighboring wordlines and bitlines is affected. A logic I is written into all the memory cells in the memory structure. An opposite voltage polarity is caused on the bitlines due to the logic 1 in the memory cells. A reverse voltage polarity stress is achieved on the wordlines by flipping the state of the lowest predecoded line (i.e., by changing the input address corresponding to that line.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective.

Abstract: Systems and methods that interface with a management system are provided. In one embodiment, a system and a method may provide a command protocol and format for communication between a network interface card (NIC) and a management device such as, for example, an intelligent management device (IMD). An interface may be adapted to allow the management device to merge its traffic with that of the NIC to provide a fully integrated management solution. The fully integrated management solution may be implemented, for example, without additional network connections.

Abstract: An optical line terminal (OLT) monitors and controls communications with a plurality of optical nodes (ONs), such as optical network units (ONUs) and/or optical network terminators (ONTs), within a passive optical network (PON), such as, but not exclusively, an Ethernet-based passive optical node (EPON). A tagging mechanism is implemented to identify an origin ON that introduces a frame into the PON segment linking the origin ON with the OLT. The origin ON produces a PON tag to associate its identifier (ON_ID) to the frame. The PON tag facilitates filtering and forwarding operations, and enables the physical layer interface (PHY) to the PON segment to emulate a point-to-point and/or shared communications link. The PON tag allows a MAC control layer to create virtual ports to traffic incoming and outgoing optical signals, and supply the virtual ports to a forwarding entity for frame filtering and forwarding.

Abstract: Die-down array integrated circuit (IC) device packages with enhanced thermal, electrical, and input/output properties are presented. A die-down array IC device package includes a heat spreader having a central cavity. A first substrate surface is coupled to the heat spreader. A central opening through the substrate overlaps the central cavity. Alternatively, the heat spreader is formed by coupling a ring-shaped body to a planar heat spreader. The first substrate surface is coupled to the ring-shaped body and the substrate central opening overlaps a central opening through the ring-shaped body. An array of electrically conductive terminals is coupled to a second substrate surface. An IC die is mounted to the heat spreader within the central cavity. Bond pads on the die are coupled to corresponding bond pads on the substrate with a plurality of wire bonds. Electrically conductive bumps on the die are coupled to corresponding bond pads on an interposer.

Abstract: An iterative multistage detection system and method for orthogonally multiplexing K channels onto a signal processing chain using N orthogonal sequences of length N. The K channels include a first set of N channels and a second set of M channels (the M channels being separate and distinct from the N channels), where K=N+M. In a first iteration, interference from the first set of N channels imparted on the second set of M channels is removed from the multiplexed signal, thereby enabling the symbol values associated with the second set of M channels to be reliably estimated. In a second iteration, interference from the second set of M channels imparted on the first set of N channels is removed from the first set of N channels, thereby enabling the symbol values associated with the first set of N channels to be reliably estimated.

Abstract: A method and associated system for effectively increasing the number of antenna elements within a multi-element antenna system through computation of a response of “virtual” antenna elements located along an antenna array. The physical elements of the array are positioned sufficiently near each other to enable synthesis of a polynomial or other mathematical expression characterizing the response of the array to receipt of an incident waveform. Values of the responses associated with the virtual antenna elements of the array may then be determined through evaluation of the synthesized polynomial or other expression. The resultant array response values associated with the virtual and physical elements of the array are then provided to an associated receiver for processing.

Abstract: A one time programmable memory cell for use in high-density memory devices is provided. The one time programmable memory cell includes a fuse device connected to a bit line and a select device and a select device connected to a row select line and to ground. The fuse device may be a thin oxide transistor having its gate connected to the bit line, its source connected to the select device, and a floating or non-existent. Alternatively, the fuse device may be a thin oxide transistor. The high density memory device includes a plurality of the one time programmable memory cells arranged in an array and adapted to be programmed using a high voltage.

Abstract: Methods, systems and computer program products to implement extensions of the Media Transport Protocol (MTP) are provided herein. The methods include opening a session between an initiator and a responder, exchanging one or more of device and system information and sending one of an operation or event based on media player application features. The operation includes one or more of a dataset, response code, operation parameter and response parameter. In an embodiment, the extensions enable the initiator and responder to manage connections efficiently between devices, send media player application information to a media player device, exchange device and system information, manage digital rights, monitor system security and specify properties within one or more extensions of MTP. These extensions may be in the form of one or more of an operation, an event, a dataset or property code.

Abstract: An architecture to compensate for the non-linear effects of magnetic media, such as magnetic disk drives, that distorts data transitions when data is written to the media and in which the non-linear distortion is data sequence dependent. In one technique a circuit is used to alter the data transitions to cancel the effects of the transition distortion. The circuit employs selected delays that that based on the data sequence to adjust the transition edge of bits of the data to provide the pre-compensation before data is written to the disk.

Abstract: A multi-port SERDES transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port SERDES transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. The ring structure of the bus provides efficient communication between the logic core and the various data ports.

Abstract: Methods, systems and computer program products to implement extensions of the Media Transport Protocol (MTP) are provided herein. The methods include opening a session between an initiator and a responder, exchanging one or more of device and system information and sending one of an operation or event based on media player application features. The operation includes one or more of a dataset, response code, operation parameter and response parameter. In an embodiment, the extensions enable the initiator and responder to manage connections efficiently between devices, send media player application information to a media player device, exchange device and system information, manage digital rights, monitor system security and specify properties within one or more extensions of MTP. These extensions may be in the form of one or more of an operation, an event, a dataset or property code.

Abstract: An apparatus is disclosed to compensate for non-linear effects resulting from the transmitter, the receiver, and/or the communication channel in a communication system. A receiver of the communication system contains an image cancellation module that compensates for images generated during the modulation and/or demodulation process. The image cancellation module includes a fine carrier correction loop to correct for frequency offsets between the transmitter and receiver. The image cancellation module includes a coarse acquisition mode and a decision directed mode. The decision directed mode allows for a larger signal-to-noise ratio for the receiver when compared against the coarse acquisition mode.

Abstract: Vector orthogonal frequency division multiplexing (VOFDM) receiver correlation matrix processing using factorization. Efficient correlation matrix processing is used to combine multiple signals into a single combined signal. This single combined signal may be viewed as being a beam form soft decision. An efficient square root factorization system and method provides for computational resource savings while, at the same time, providing for greater precision of the overall computational results. By reducing intermediate variable calculation dynamic ranges, the overall calculation becomes more precise. Particularly within fixed-point arithmetic applications, a reduction in dynamic range of the intermediate variable calculations provides for a significant increase in final calculation precision.

Abstract: A network device for minimizing latency and correcting errors associated with information transmitted from an external memory device. The network device includes a management unit for requesting information stored on at least one external memory device. The network device also includes a command unit for transmitting a request from the management unit to the external memory device. The command unit maintain at least one counter that is associated with current requests and compares the at least one counter to at least one predefined threshold in order to throttle the management unit when the at least one counter exceeds the at least one threshold. The network device further includes means for aligning information from the at least one external memory device with information transmitted from the command unit to the management unit and for ensuring that aligned information is accurate.

Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.