Abstract: In a method and system for 3D comb synchronization and alignment of standard and non-standard video signals, a coarse synchronization is performed on a bottom frame, a current frame, and a top frame based on a bottom frame field count. The current frame is assigned the frame transferred immediately prior to a bottom frame whereas the top frame is assigned the frame transferred two frames. A current frame window signal and a top frame window signal may be used to lock the current frame and the top frame to a bottom frame vertical sync signal. After coarse synchronization, the video frames are finely aligned by correlating a phase difference between the subcarrier signals in each frame and modifying the phase difference until the correlation results in a specified phase locked value range. This method and system may facilitate the handling of video stream switching and non-standard data streams.

Abstract: An electrically and mechanically enhanced die-down tape substrate ball grid array (BGA) package substrate is described. An IC package includes a substrate that has a first surface. The first surface has a central opening. A stiffener/heat spreader has a first surface. The first surface of the stiffener has a central ground ring. The first surface of the stiffener is coupled to a second surface of the substrate. The central opening has an edge. The edge includes at least one of the following: (a) a protruding edge portion that extends across at least a portion of the central ground ring, (b) a recessed edge portion that exposes a portion of the central ground ring, or (c) a hole proximate to the edge, wherein the hole exposes a portion of the central ground ring.

Abstract: A receiver circuit of the modem is coupled to receive a continuous analog signal from a communication channel. This analog signal includes both packet and idle information. A burst mode protocol is also provided, in which packets of digital information are modulated by a transmitter circuit of the modem, thereby converting the packets of digital information into analog signal bursts of discrete duration. These analog signal bursts are transmitted from the transmitter circuit to a telephone line. A receiver circuit monitors the telephone line to detect the analog signal bursts. Upon detecting the presence of the analog signal bursts on the telephone line, the receiver circuit demodulates the analog signal bursts using full processing capabilities of the receiver circuit. However, upon detecting the absence of the analog signal bursts on the telephone line, the demodulating function of the receiver circuit is disabled.

Abstract: A wireless network card includes an adaptable antenna connection structure that includes connections for one or more internal antennas and for one or more Radio Frequency (RF) connectors that may be coupled to one or more external antennas. A Printed Circuit Board (PCB) and electronic components located thereon form the wireless network card. The PCB includes a removable portion that, when removed, leaves an opening that receives an RF antenna connector. When the PCB is used to create a client wireless network card, one or more surface mount antennas are mounted on the PCB and coupled to surface mount antenna conductive pads formed thereon. The wireless network card may include (1) the surface mount antenna; (2) the RF connector; or (3) both the surface mount antenna and the RF connector.

Abstract: A channel select filter having channel equalization includes a first low pass filter stage, a gain stage, a subtraction module, and a second low pass filter stage. The first low pass filter stage is operably coupled to filter input signals to produce first low pass filtered signals. The gain stage is operably coupled to adjust gain of the input signals to produce gained input signals. The subtraction module is operably coupled to subtract the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage is operably coupled to filter the first stage signals to produce channel selected signals.

Abstract: A system and method of analyzing a powered device (PD) in a Power-over-Ethernet (PoE) system are presented. The system includes an Ethernet interface having a physical layer (PHY) chip capable of providing a signal pulse in addition to physical layer 1 functions. The system further includes a pulse transformer, coupled to the PHY chip, capable of relaying the signal pulse provided by the PHY chip to the PD via the transmit line and a second PHY chip. The first PHY chip receives one or more return pulse signals from the PD, analyzes characteristics such as voltage and/or frequency of the return pulse signal(s), and determines attributes of the PD based on those characteristics. The attributes can include powered device validity and power classification. A method of supplying power to a PD is also presented.

Abstract: A home network, in one embodiment including a home wiring system; a demarcation point unit in electrical communication with the home wiring system; and a home network module in electrical communication with the home wiring system. The home network module is adapted for connection to a home electronic device. The demarcation point unit passes data to and receives data from the home electronic device through the home network module.

Abstract: A balun that includes a first conductor, a second conductor, and a third conductor. The first conductor has a first length. The first conductor also has a first end connected to a first balanced power amplifier output port. The second conductor has substantially the same first length. The second conductor also includes a first end connected to a second balanced power amplifier output port and a second end connected to a second end of the first conductor. The third conductor has substantially the same first length. The third conductor has a first end connected to an antenna port and a second end connected to a ground potential.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A Galois field multiplier array includes a 1st register, a 2nd register, a 3rd register, and a plurality of multiplier cells. The 1st register stores bits of a 1st operand. The 2nd register stores bits of a 2nd operand. The 3rd register stores bits of a generating polynomial that corresponds to one of a plurality of applications (e.g., FEC, CRC, Reed Solomon, et cetera). The plurality of multiplier cells is arranged in rows and columns. Each of the multiplier cells outputs a sum and a product and each cell includes five inputs. The 1st input receives a preceding cell's multiply output, the 2nd input receives at least one bit of the 2nd operand, the 3rd input receives a preceding cell's sum output, a 4th input receives at least one bit of the generating polynomial, and the 5th input receives a feedback term from a preceding cell in a preceding row. The multiplier cells in the 1st row have the 1st input, 3rd input, and 5th input set to corresponding initialization values in accordance with the 2nd operand.

Abstract: A communication system includes a link module having a first serial interface for interfacing to a serial link. The link module also including a second serial interface. The system also includes a Media Access Control (MAC) module including a parallel interface. The system also includes a converter module, coupled between the parallel interface and the second serial interface, configured to convert symbols, transferred between the parallel interface and the second serial interface, between a parallel format at the parallel interface and a serial format at the serial interface.

Abstract: A method of parameter estimation in a shared channel communications system includes the steps of receiving a preamble including a first sequence corresponding to a sequence having zero autocorrelation, a second sequence having zero autocorrelation, and a third sequence having zero autocorrelation, performing a coarse carrier frequency estimate based on the first sequence, and performing a fine carrier frequency estimate based on the second and third sequences.

Abstract: An apparatus, system, and method for assembling a ball grid array (BGA) package is described. A stiffener/heat spreader is provided. A substrate has a first surface and a second surface. The substrate has a central window-shaped aperture that extends through the substrate from the first substrate surface to the second substrate surface. The first substrate surface is attached to a surface of the stiffener/heat spreader. A portion of the stiffener/heat spreader is accessible through the central window-shaped aperture. An IC die has a first surface and a second surface. The first IC die surface is mounted to the accessible portion of the stiffener/heat spreader. A drop-in heat spreader has a surface that is mounted to the second IC die surface.

Abstract: A line driver for generating 10 BT signals is disclosed. Digital symbols to be transmitted via a 10 BT Ethernet line are converted by a digital-to-analog converter into a corresponding analog voltage signal, which is fed into an active output impedance line driver. The digital-to-analog converter also receives a reference voltage reflecting variations of the supply voltage and adjusts its output signal accordingly to provide a deliberately variable analog voltage signal to the line driver.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device and includes a WLAN interface, a transcoder, and a switch box. The WLAN interface wirelessly communicates with at least one WLAN device to receive inbound packetized audio data from the at least one WLAN device and to transmit outbound packetized audio data to the at least one WLAN device. The transcoder receives the inbound packetized audio data and converts the inbound packetized audio data to inbound Pulse Code Modulated (PCM) WLAN audio data. The WLAN interface also receives outbound PCM WLAN audio data and converts the outbound PCM WLAN audio data to the outbound packetized audio data. The switch box operably couples between the transcoder and a PCM bus, to which an audio COder/DECoder (CODEC) couples. A speaker and a microphone coupled to the audio CODEC.

Abstract: A method for designing an interpolation filter begins by partitioning interpolation filtering into a plurality of interpolation filtering stages that are cascaded together. Each of the plurality of interpolation filtering stages includes an up sampling stage and a filtering stage. The method continues by manipulating a first one of the interpolation filtering stages based on a first digital signal processing identity to produce a first equivalent interpolation filtering stage. The method continues by manipulating a second one of the interpolation filtering stages based on the first digital signal processing identity to produce a second equivalent interpolation filtering stage. The method continues by simplifying the first and second equivalent interpolation filtering stages to produce at least a simplified portion of the interpolation filter.

Abstract: According to the present invention, the multiple processor device determines routing for a plurality of data segments. In determining the routing, the multiple processor device first receives the plurality of data segments. The plurality of data segments include multiplexed data fragments from at least one of a plurality of virtual channels. Further, a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The multiple processor device then applies at least one routing rule to one of the plurality of data segments to produce at least one result corresponding to the one of the plurality of data segments. The multiple processor device then interprets the at least one result to determine whether sufficient information is available to render a routing decision for the one of the plurality of data segments.

Abstract: Methods and apparatus are provided for improving ARC4 processing in a cryptography engine. A multiple ported memory can be used to allow pipelined read and write access to values in memory. Coherency checking can be applied to provide that read-after-write and write-after-write consistency is maintained. Initialization of the memory can be improved with a reset feature occurring in a single cycle. Key shuffle and key stream generation can also be performed using a single core.

Abstract: A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats is disclosed. In particular, the system is able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations. The system includes carrier and timing recovery loops adapted to operate on an enhanced pilot signal as well as decision directed carrier phase recovery loops. Phase detectors operate on I and Q rail signals, or generate a Q rail from a Hilbert transform of the I rail. Decision directed loops incorporate a trellis decoder in order to operate on sequence estimated decisions for improved reliability in poor SNR environments.

Abstract: A system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In an embodiment of the present invention a two-level memory coherency scheme is implemented for use by multiple processors operably coupled to multiple buses in the same integrated circuit. A control device, such as node controller, is used to control traffic between the two coherency levels. In an embodiment of the invention the first level of coherency is implemented using a “snoopy” protocol and the second level of coherency is a directory-based coherency scheme.