Abstract: A system and method for accelerated handling of masked store operations in a processor or processor-based system/chip are described. A set of instructions that support a store operation under a per-byte predicate mask is provided. The invention accelerates the handling of small transfers at arbitrary alignments, such as those used by xDSL modems to deal with ATM cells or Reed Solomon codewords.

Abstract: A voice data and RF integrated circuit (IC) includes a memory module that stores a least one application as a plurality of operational instructions, the at least one application having a plurality of power modes that each correspond to one of a plurality of use characteristics. A processing module executes the plurality of operational instructions and that determines a selected one of the plurality of power modes based on current use characteristics of the at least one application, and generates a power mode signal based on the selected one of the plurality of power modes. An on-chip power management circuit receives the power mode signal and that generates a plurality of power supply signals based on the power mode signal.

Abstract: An audio codec integrated with baseband processing and RF on a single IC chip. The audio codec may be implemented in a variety of wireless transceivers, such as cell phones, to offer voice, data and/or music functions. The codec also has monaural and stereo channels for audio output, as well as stereo inputs.

Abstract: A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what, if any, errors have occurred. If the real-time system, such as a transceiver in a communication system, has adaptive components, the status of the adaptive components is used to estimate the condition of any external systems coupled to the real-time system.

Abstract: A system and method for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip.

Abstract: Multiple channel synchronized clock generation scheme. A novel approach is presented herein in which synchronized clock signals are generated that can be used in parallel processing of deserialized signals. When a serial input signal is received, it can be deserialized into a plurality of parallel signals, and each of these parallel signals can be processed at a frequency that is lower than the frequency of the serial signal. Overall, the frequency at which all of the parallel signals are processed can be the same or substantially close to the frequency of the serial signal, so that throughput within a communication system is not compromised or undesirably reduced. This novel approach is operable to perform independent adjustment of the operational parameters within an apparatus that is operable to perform multiple channel synchronized clock generation (e.g., phase rotation and/or division of signals within each of the individual channels can be adjusted independently).

Abstract: An ATM network traffic shaper is implemented in hardware. The traffic shaper shapes transmit data on one or more virtual circuits (VCs) according to the specified quality of service (QoS) parameters. Thus, the traffic shaper provides for the delivery of associated data cells in accordance with the specified QoS parameters. The traffic shaper is scalable in that the number of supported VCs can be increased with a relatively small increase in the size of the device and associated logic gates. The traffic shaper supports constant bit rate (CBR), variable bit rate (VBR), and unknown bit rate (UBR) service types and generates cell transmit requests with zero cell delay variation (CDVT). The traffic shaper also provides very high resolution in terms of bit rate specification. Varying shaping resolutions are achieved by varying a shaping interval time (SIT) generated by a SIT counter.

Abstract: A method for generating a preamble of a frame for a wide-bandwidth channel wireless communication begins by generating a legacy carrier detect field. The method continues by generating a channel sounding field, wherein the channel sounding field includes a plurality of tones within the wide-bandwidth channel, wherein a first set of the plurality of tones corresponds to tones of a legacy channel sounding field. The method continues by generating a legacy signal field, wherein, in time, the legacy signal field follows the channel sounding field, which follows the legacy carrier detect field.

Abstract: A technique to adjust gain and DC level of current DAC signals with offset to generate a voltage signal that is used to control power level of a power amplifier. One or more current mirrors from a set of current mirrors is programmably selected to set gain of a current-to-voltage conversion stage. A second set of current mirrors used to adjust DC level current is oppositely tracked to the current mirrors used for the gain. The opposite tracking allows for deactivation (or activation) of respective current mirrors in the second set in response to activation (or deactivation) of respective gain setting current mirrors to maintain a substantially constant DC level when gain values are changed. An additional set of current mirrors allows for independent compensation of DC offsets.

Abstract: A system and method for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip.

Abstract: During start-up of a circuit having a high voltage supply and a low voltage supply, a backup bias generator (BBG) is used to avoid burnout and exceeding a breakdown voltage. The high voltage supply is powered on before the low voltage supply. The BBG generates bias in response to the high voltage supply being powered on. Once the low voltage supply is powered on and is stable, the BBG is shut down so that it does not interfere with normal operation of the circuit. The circuit can be separated into high and low supply domains without breakdown issues during power start-up, allowing for power and area optimization.

Abstract: Methods and systems for 3D comb filtering of a video signal are provided. Aspects of the method may include generating a plurality of interpolated pixels for corresponding video samples for a first video frame, determining at least one direction of least bandwidth among the video samples and the interpolated pixels, and blending combing according to the determined direction of least bandwidth. A plurality of interpolated pixels for corresponding video samples may be generated in a first pixel line of the first video frame. The plurality of interpolated pixels in the first pixel line may be generated, so that each of the plurality of interpolated pixels in the first pixel line is one quarter cycle phase-shifted from a corresponding adjacent pixel in the first pixel line.

Abstract: Aspects of the invention provide a method and system for a communication bus for resetting one or more devices connected to the bus. The transceiver bus (620) may include a single serial data line (616), a single serial clock line (614) and a single reset line (612). A status of a slave device coupled to the transceiver bus (620) may be determined by a master device. Based on the status of the slave device, the master device may execute a forced reset or a normal reset. In a case where a device may be unresponsive, the master device may execute a forced reset. Additionally, in a case where a device is responsive but requires resetting, the master device may execute a normal reset and selectively reset a slave device requiring reset.

Abstract: Methods and systems for 3D bidirectional comb filtering of a video signal are provided. Aspects of the method may include generating a plurality of interpolated pixels for a current line, a next line and a previous line in a current frame. A plurality of interpolated pixels may be generated in a previous frame, which corresponds to the interpolated pixels in the current frame. A plurality of interpolated pixels may be generated in a next frame, which corresponds to the interpolated pixels in the current frame. At least one direction of least bandwidth may be determined among at least a portion of all the generated interpolated pixels and true pixels in the current frame. Combing may be blended according to the determined at least one direction of least bandwidth.

Abstract: A method and system for pulse code modulation (PCM) audio ramp and decay function may comprise receiving at least one control signal which indicates whether to enable a ramp-up function or a decay function. When the ramp-up function is enabled, an audio input signal may be modified such that an input low to high transition may make a more gradual transition from low to high at the output, and when the decay function is enabled the audio input signal may be modified such that an input high to low transition may make a more gradual transition from high to low at the output. These functionalities may reduce unwanted noise generated when there is a sudden high to low transition, or a sudden low to high transition, in audio signals.

Abstract: A phase lock loop comprising a plurality of voltage controlled oscillators is presented herein. The phase lock loop can provide a wide range of output frequencies with low jitter. Additionally, the phase lock loop can be incorporated into a clock multiplier unit and a clock and data recovery unit.

Abstract: A high frequency integrated circuit (IC) pad configuration includes a first IC pad, an inductor, and a second IC pad. The first IC pad is directly coupled to input or output a high frequency signal, wherein no electrostatic discharge (ESD) protection circuitry is directly coupled to the first IC pad. The inductor includes a first node and a second node, wherein the first node of the inductor is directly coupled to the first IC pad, and wherein the inductor has a high impedance with respect to a desired input or desired output impedance of the first IC pad at frequencies of the high frequency signal. The second IC pad is directly coupled to a power connection, to the second node of the inductor, and to an ESD protection circuit, wherein the inductor and the ESD protection circuit of the second IC pad substantially provides ESD protection for the first IC pad.

Abstract: An iterative multistage detection system and method for orthogonally multiplexing K channels onto a signal processing chain using N orthogonal sequences of length N. The K channels include a first set of N channels and a second set of M channels (the M channels being separate and distinct from the N channels), where K=N+M. In a first iteration, interference from the first set of N channels imparted on the second set of M channels is removed from the multiplexed signal, thereby enabling the symbol values associated with the second set of M channels to be reliably estimated. In a second iteration, interference from the second set of M channels imparted on the first set of N channels is removed from the first set of N channels, thereby enabling the symbol values associated with the first set of N channels to be reliably estimated.

Abstract: A mixer is disclosed that includes first and second transconductance modules that, in one embodiment, includes MOSFETs configured to receive a plurality of signals that are to be mixed and a selectively coupled auxiliary current source to inject an auxiliary current into the second transconductance module approximately at or near a zero-crossing point in order to reduce flicker noise and other noise introduced into an output signal during switching. Accordingly, as a first transconductance module approaches a zero-crossing, auxiliary current is injected to reduce the current produced therefrom thereby reducing flicker noise. In a differential mixer, the amount of current produced from a transistor pair to which the signal cycle is being switched is also reduced thereby reducing noise from the transistor pair that is turning on for the next portion of a signal cycle.

Abstract: Systems and methods that provide channel bonding in multiple antenna communication systems are provided. In one embodiment, a method for signal transmission over a plurality of antennas of a transmitter may include, for example, one or more of the following: demultiplexing an input signal into a plurality of signal components; assigning each of the signal components to one of a plurality of logical channels; weighting each of the signal components with transmit baseband weight values; combining ones of the resultant weighted signal components to form a plurality of transmit weighted signals, each of the plurality of transmit weighted signals being assigned to one of the plurality of logical channels; and combining groups of the plurality of transmit weighted signals to form a plurality of output signals capable of being used to generate a plurality RF output signals.