Abstract: System and method for integrating communications between two switches. The system includes a first switch, a second switch and a CPU. The first switch has a first plurality of ports, and the second switch has a second plurality of ports. The CPU is coupled to the first switch and the second switch, and is configured to control and program the first and second switch. A port of the first plurality of ports, as a first link port, is coupled to a port of the second plurality of ports, as a second link port. The first plurality of ports are designated by a first numbering scheme, the second plurality of ports are designated by a second numbering scheme, and the first and second link ports each have a tag insertion unit, a processing unit and a removing unit, for inserting an inter-stack tag, processing the packet, and removing the inter-stack tag.

Abstract: A system and method for matching chip and package terminals and for packaging integrated circuits. Various aspects of the present invention may comprise receiving as input a first list of chip terminal identifiers and a second list of package terminal identifiers. The first and second lists may be analyzed with a first string-matching algorithm to determine a first set of matching pairs of chip terminals and package terminals. The first and second lists may also be analyzed with a second string-matching algorithm to determine a second set of matching pairs of chip terminals and package terminals. The first and second sets of matching pairs may be compared to identify common matching pairs between the first and second sets of matching pairs. An indication of the common matching pairs may then be output.

Abstract: A node comprises one or more resources and a register programmable with an indication during use. The one or more resources are addressed with addresses within a local region of an address space. The indication identifies a second region of the address space that is aliased to the local region, and other nodes address the one or more resources using addresses in the second region.

Abstract: A method is presented that monitors the quality of a communications channel. The method includes receiving a data signal and establishing a zero reference phase of the received data signal. The method further includes generating a phase-shifted data signal by phase shifting the received data signal relative to the zero reference phase, and sampling the phase-shifted data signal for one or more phase-shift positions. A zero reference phase is reestablished between sampling at each of the phase-shift positions. The method also includes detecting bit errors in the phase-shifted data signal at each of the phase-shift positions in order to provide a communications channel quality measurement. In an embodiment, the method includes generating an eye diagram according to a count of detected bit errors relative to a count of detected bits. The eye diagram characterizes the quality of the communications channel.

Abstract: Tracing instruction flow in an integrated processor by defeaturing a cache hit into a cache miss to allow an instruction fetch to be made visible on a bus, which instruction would not have been made visible on the bus had the instruction fetch hit in the cache. The defeature activation is controlled by use of a defeature hit signal bit in a defeature register, and in which the bit may be programmed.

Abstract: An ATM network traffic shaper is implemented in hardware. The traffic shaper shapes transmit data on one or more virtual circuits (VCs) according to the specified quality of service (QoS) parameters. Thus, the traffic shaper provides for the delivery of associated data cells in accordance with the specified QoS parameters. The traffic shaper is scalable in that the number of supported VCs can be increased with a relatively small increase in the size of the device and associated logic gates. The traffic shaper supports constant bit rate (CBR), variable bit rate (VBR), and unknown bit rate (UBR) service types and generates cell transmit requests with zero cell delay variation (CDVT). The traffic shaper also provides very high resolution in terms of bit rate specification. Varying shaping resolutions are achieved by varying a shaping interval time (SIT) generated by a SIT counter.

Abstract: A phase locked loop includes a detection module, a control conversion module, a controlled oscillation module, a divider module, and a power distribution module. The detection module is operably coupled to produce a difference signal based on a difference between a reference oscillation and a feedback oscillation. The control conversion module is operably coupled to convert the difference signal into a control signal. The controlled oscillation module is operably coupled to produce an output oscillation based on the control signal. The divider module is operably coupled to produce the feedback oscillation based on the output oscillation. The power distribution module is operably coupled to receive a supply voltage and to provide an individual supply voltage to at least one of the detection module, the control conversion module, the controlled oscillation module, and the divider module to optimize at least one of performance and power consumption of the phase locked loop.

Abstract: A method for synchronizing clocks in a packet transport network. The method comprises, receiving an external network clock at a central packet network node and transmitting timing information to a plurality of packet network devices, the timing information based upon the external network clock. The method further comprises, transmitting and receiving data that is synchronized to the timing information to a plurality of connected packet network devices. And finally, delivery of packets to an external interface via a packet network that contains data synchronized to the external network clock.

Abstract: Methods and systems for time constant for a 3D comb filter of a video signal are provided. Aspects of the method may include assigning a weight to a 3D comb mesh value. Combing may be blended according to the assigned weight of the 3D comb mesh value. The weighted 3D comb mesh value may be accumulated in order to generate accumulated mesh value. If the accumulated mesh value exceeds a saturation value, the accumulated mesh value may be reduced to the saturation value. If the 3D comb mesh value is smaller than a first threshold value, the accumulated mesh value may be reset to zero. A multiplier may be generated according to the accumulated mesh value. If the accumulated mesh value is between a second threshold value and a third threshold value, the multiplier may be blended.

Abstract: Method and system for translating Verilog to C++ are provided herein. Aspects of the method for translating may include searching for a Verilog pattern in a Verilog file and substituting the Verilog pattern with a C++ language expression, wherein the C++ language expression is associated with the same functionality as the Verilog pattern. It may be identified whether the Verilog file comprises at least one of a task library, a main driver, and a driver module. If the Verilog file comprises a task library, a Verilog task within the task library may be identified; and the Verilog task may be translated into a C++ function. If the Verilog file comprises a main driver, a C++ interface header may be inserted in the Verilog file.

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract: A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: Combined LDPC (Low Density Parity Check) encoder and syndrome checker. A novel approach is presented by which the encoding processing and at least a portion of the decoding processing of an LDPC coded signal can be performed using a shared circuitry. The LDPC encoding processing and syndrome calculation operations (in accordance with the LDPC decoding processing) can be performed using a common circuitry having a portion of which whose connectivity is only slightly modified depending on whether encoding or decoding is being performed. To effectuate this selection (between encoding and decoding), any of a variety of means can be employed including the use of multiplexers that are operable to select a first connectivity (for encoding) and a second connectivity (for decoding). This can result in a hardware savings of space, cost, and complexity since a shared circuitry can perform both encoding and at least part of the decoding processing.

Abstract: Embodiments include a decision feedback equalizer (DFE) circuit, including at least one reorder block configured to reorder a set of current sliced bit values based on one or more previous sliced bit values, and a selector configured to select one of the reordered current sliced bit values as a DFE output based on a group of non-adjacent DFE outputs.

Abstract: A method for classifying an incoming packet. The method includes maintaining a database associated with patterns of fields, where the fields can be network addresses. The database can be developed by mapping each pattern to a unique numeric identifier. The number of unique numeric identifiers is equal to the number of patterns, and the size of each unique numeric identifier is substantially smaller than the field of each pattern. The database can be further developed by determining a range of one or more of the unique numeric identifiers to be associated with each pattern. The range for each pattern can be bounded by a minimum unique numeric identifier and a maximum unique numeric identifier. The method also includes using a field of the incoming packet to determine an associated identifier for that field, where the associated identifier is equal to one of the unique numeric identifiers.

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract: A radio frequency identification (RFID) decoding subsystem includes a pre-decode module and a decode module. The pre-decode module is coupled to process down-converted RFID signals into pre-decoded baseband data. The decode module is coupled to: enable a counting process based on the pre-decoded baseband data to produce a count resultant; and compare the count resultant with a threshold at a data bit interval to produce decoded RFID data.

Abstract: A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what, if any, errors have occurred. If the real-time system, such as a transceiver in a communication system, has adaptive components, the status of the adaptive components is used to estimate the condition of any external systems coupled to the real-time system.

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract: Programmable integrated Digital Satellite Equipment Control (DiSEqC) transceiver. The DiSEqC functionality is integrated onto a semiconductor device. Rather than perform the DiSEqC protocol in software, the DiSEqC protocol is implemented in hardware thereby providing more reliable demodulation and improved robustness. The device's functionality may employ much more reliable communication schemes that are enabled by the hardware/integrated approach of implementing the DiSEqC protocol. The integrated approach allows extensive programmability of the various operational parameters thereby greatly improving the ease of future backward compatibility with legacy devices; devices employing this integrated DiSEqC functionality may be easily updated to conform to future enhancements of the DiSEqC protocol.