Abstract: A method of accommodating aberrant behavior in wireless devices in a wireless network includes the steps of establishing communication with at least one wireless device, monitoring signals received from the at least one wireless device, determining characteristics of the at least one wireless device based on the monitored signals, comparing the determined characteristics with prescribed characteristics for wireless devices exhibiting aberrant behavior and altering settings to accommodate the at least one wireless device, when the determined characteristics match the prescribed characteristics.

Abstract: Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.

Abstract: A low profile Planar Inverted-F Antenna (PIFA) comprises a radiating strip, an inductive tuning portion, a vertical feed portion, and a retracted ground plane. The radiating strip is approximately parallel to the ground plane and is suspended above the ground plane by the feed element at a certain distance. Further, the radiating strip, in part or entirely, overhangs the ground plane. In this way, the radiating strip may be suspended very close to the ground plane, but yet exhibits a large bandwidth.

Abstract: A voltage measurement circuit is operative to measure a high voltage AC signal and includes a capacitive divider circuit and a compensator circuit. The capacitive divider circuit includes first and second inputs, across which, in use, is received a high voltage AC signal and also includes second and third capacitors. First and second plates of each of the first, second and third capacitors are defined by conductive layers of a printed circuit board and the dielectric of each of the first, second and third capacitors being defined by a non-conducting part of the printed circuit board. A compensator circuit has a configurable transfer function and includes an input connected across the first and second plates of the third capacitor and an output. The compensator circuit is operative to change a voltage received at its input in accordance with the transfer function and to provide the changed voltage at its output.

Abstract: A system and method for dynamically swapping master and slave physical layer devices (PHYs) in energy efficient Ethernet (EEE). A physical layer communication mechanism can be used to dynamically reassign the master/slave assignments to facilitate the asymmetric application of EEE to a link.

Abstract: There is presented a circuit and a related method for adaptively supplying Power over Ethernet (PoE) by a power sourcing equipment. The circuit comprises first and second power channels coupled to first and second network interfaces of the power sourcing equipment. A shunt device is operated to identify a maximum power characteristic of a powered device. The first power channel provides a first current to the powered device through the first network interface if the maximum power characteristic does not exceed a power threshold. The circuit provides another current to the powered device through the first network interface if the maximum power characteristic is greater than the power threshold. Various embodiments of the present invention may provide a second current to another powered device through the second network interface if the maximum power characteristic of the first and second powered devices does not exceed the power threshold.

Abstract: A direct sampling tuner includes a low noise amplifier and an optional dynamically configurable band pass filter coupled to the low noise amplifier. The optional filter is configured to pass a selected band of channels. The tuner further includes a relatively high accuracy, multi-bit analog-to-digital converter (“ADC”) coupled to the LNA or to the optional dynamically configurable band pass filter. The ADC operates at greater than about twice a frequency of a sampled signal. The ADC directly samples the spectrum of the selected channels at the Nyquist rate, thus avoiding image problems presented by conventional tuners.

Abstract: An integrated circuit (IC) includes a baseband processing module and a radio frequency (RF) section. The baseband processing module is coupled to convert outbound data into amplitude modulation information and phase modulation information when the IC is in a cellular data mode and to convert an outbound radio frequency identification (RFID) signal into RFID amplitude modulation information when the IC is in an RFID mode. The RF section is coupled to generate an outbound RF data signal in accordance with the amplitude modulation information and the phase modulation information when the IC is in the cellular data mode and to generate an outbound RF RFID signal in accordance with the RFID amplitude information when the IC is in the RFID mode.

Abstract: A network device for generating an expanded long training sequence with a minimal peak-to-average ratio. The network device includes a signal generating circuit for generating the expanded long training sequence. The network device also includes an Inverse Fourier Transform for processing the expanded long training sequence from the signal generating circuit and producing an optimal expanded long training sequence with a minimal peak-to-average ratio. The expanded long training sequence and the optimal expanded long training sequence are stored on more than 52 sub-carriers.

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: A signal level crossing detector circuit includes a DC isolator and a detector circuit. The DC isolator has at least a first input, which is operable to receive a high voltage AC signal, and at least a first capacitor, a first plate of the first capacitor being electrically connected to the first input. The detector circuit is operable at a low voltage and has at least a first detector input, the first detector input being electrically connected to a second plate of the first capacitor, the low voltage detector circuit being operable to provide a change in output signal in dependence on a high voltage AC signal on the first input crossing a predetermined signal level. The signal level crossing detector may be single ended or differential.

Abstract: An RF front-end includes a transmit adjust module, a PA module, an antenna coupling circuit, a LNA module, and a receive adjust module. The transmit adjust module adjusts coordinates of up-converted analog signals when in a first transmit mode and adjusts coordinates of a plurality of up-converted analog signals when in a second transmit mode to produce to produce multiple adjusted up-converted signals and a plurality of adjusted up-converted signals, respectively, which are subsequently amplified by the PA module. The antenna coupling circuit provides the multiple or the plurality of outbound RF signals to at least some of a plurality of antennas depending on the transmit mode and provides multiple or a plurality of inbound RF signals at least some of the plurality of antennas to the LNA module based on a receive mode. The receive adjust module adjusts coordinates of the multiple or plurality of amplified inbound RF signals based on the receive mode.

Abstract: A method for generating a preamble of a frame for a multiple input multiple output (MIMO) wireless communication begins by, for each transmit antenna, generating a carrier detect field. The method continues by, for a first grouping of the transmit antennas, generating a first guard interval following the carrier detect field; and generating at least one channel sounding field. Continuing, the method applies cyclical shift prior to transmission via the first grouping of the transmit antennas. When the MIMO wireless communication includes more than the first grouping of the transmit antennas, for another grouping of the transmit antennas. For the another grouping of the transmit antennas, generating at least one other channel sounding field. The method proceeds by generating the first guard interval prior to the at least one other channel sounding field, and applying another cyclical shift prior to transmission via the another grouping of the transmit antennas.

Abstract: A wireless local area network (WLAN) transmitter includes a baseband processing module and a plurality of radio frequency (RF) transmitters. The baseband processing module is operably coupled to process data by scrambling the data in accordance with a pseudo random sequence to produce scrambled data. The processing of the data continues by selecting one of a plurality of encoding modes based on a mode selection signal. The processing of the data continues by encoding the scrambled data in accordance with the one of the plurality of encoding modes to produce encoded data. The processing of the data continues by determining a number of transmit streams based on the mode selection signal. The processing of the data further continues by converting the encoded data into streams of symbols in accordance with the number of transmit streams and the mode selection signal.

Abstract: Aspects of a method and system for transmission and/or reception of signals utilizing a delay circuit and a DDFS are provided. In this regard, a first signal may be delayed by 90°, via a plurality of delay elements and variable capacitance, to generate a second signal. The first and second signal may be mixed to generate a first LO signal, which may be utilized for a first frequency conversion. A second LO signal may be generated via a DDFS and may be utilized for a second frequency conversion. A digital input word of the DDFS, a value of the variable capacitance, and/or at least a portion of the delay elements, may be programmatically controlled based on a desired frequency for transmission and/or desired frequency for reception. The first frequency conversions may be up-conversions and/or down-conversions to/from baseband, one or more intermediate frequencies, and/or RF.

Abstract: An antenna includes a planar antenna section. A resonator grid includes a plurality of resonators in a planar array to electromagnetically enhance the performance of the plan antenna section.

Abstract: In a wireless device, a method and system for a baseband receiver interface including analog and digital components are provided. An analog or a digital interface may be selected for a I/Q data signal received from a front-end receiver. The analog interface may be a conventional RF or a VLIF interface. The I/Q data signal may be digitized when received from the analog interface and saturation detection may be used during digitization of the I/Q data signal. When the analog interface is the VLIF interface, a derotator may be used to remove the VLIF frequency. The derotator may be based on a CORDIC algorithm. The I/Q data signal may be converted from serial to parallel format when received from the digital interface. The received I/Q data signal may be decimated before transferred to a baseband processor.

Abstract: A network device includes at least one first network port, at least one second network port, a MUX unit and a switching unit. The MUX unit is connected to the at least one first network port. The MUX unit includes a trunk circuit and an output. The trunk circuit is configured to aggregate data packets received at the at least one first port into a trunk group and to output trunked data packets to the output. The switching unit is connected to the output of the MUX unit and to the at least one second network port. The switching unit is configured to switch the trunked data packets to the at least one second network port.

Abstract: The present invention includes operational amplifier for an active pixel sensor that detects optical energy and generates an analog output that is proportional to the optical energy. The active pixel sensor operates in a number of different modes including: signal integration mode, the reset integration mode, column reset mode, and column signal readout mode. Each mode causes the operational amplifier to see a different output load. Accordingly, the operational amplifier includes a variable feedback circuit to provide compensation that provides sufficient amplifier stability for each operating mode of the active pixel sensor. For instance, the operational amplifier includes a bank of feedback capacitors, one or more of which are selected based on the operating mode to provide sufficient phase margin for stability, but also considering gain and bandwidth requirements of the operating mode.

Abstract: An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.