Abstract: Disclosed is an amplifier circuit configured to amplify a pulse stream. The amplifier circuit comprises a switching block including a first switch operable to couple an output node of the switching block to a positive reference voltage, a second switch operable to couple the output node to a ground reference voltage and a third switch operable to couple the output node to a negative reference voltage. The amplifier circuit is configured to amplify the pulse stream into an amplified signal detectable at the output node such that the amplified signal has a common-mode voltage level substantially equal to zero volts. In one embodiment, the amplifier circuit is configured to amplify the pulse stream in accordance with a Class-D amplification scheme. In one embodiment, the output node can be directly connected to a load device without a DC blocking capacitor being interposed between the output node and the load device.

Abstract: A system and method for unique identifier exchange during auto-negotiation. Wired networks can include non-conformant bridges and/or repeaters that can erroneously forward link protocol frames such as LLDP. These present a problem for higher layer protocols that attempt to manage properties of the link. The unique identifiers exchanged during auto-negotiation can be passed up to higher layers for an integrity check of unique identifiers exchanged using higher layer protocols.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The spoke modules include a plurality of interface circuits each having a hardware address. A memory module stores the hub software and hub data and configuration data. The hub software includes a plurality of driver modules corresponding to the plurality of interface circuits. The processing module executes boot firmware to configure the plurality of driver modules based on the hardware address of each of the plurality of interface circuits.

Abstract: Systems and methods that manage memory are provided. In one embodiment, a system for communications may include, for example, a memory management system that may handle a first application employing a virtual address based tagged offset and a second application employing a zero based tagged offset with a common set of memory algorithms.

Abstract: A frame format for high data throughput wireless local area network transmissions includes a first preamble segment, a second preamble segment, and a variable length data segment. The first preamble segment includes at least one training sequence and a high throughput channel indication. The second preamble segment includes a high data throughput training sequence when the high throughput channel indication is set and includes a null segment when the high data throughput training sequence is not set.

Abstract: A system and method for controlling the delivery of power to a powered device in a Power over Ethernet Broad Reach (PoE-BR) application. Cabling power loss in a PoE-BR application is related to the resistance of the cable itself. A PHY can be designed to measure electrical characteristics (e.g., insertion loss, cross talk, length, etc.) of the Ethernet cable to enable determination of the cable resistance. The determined resistance in a broad reach cable can be used in increasing a power budget allocated to a power source equipment port.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The hub module includes a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules by receiving a clock request signal from a corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces, generating at least one of the plurality of clock signals in response to the clock request signal; and sending the at least one of the plurality of clock signals to the corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces.

Abstract: A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports.

Abstract: A method and system for decoding control data in GSM-based systems using inherent redundancy and physical constraints are presented. At least one estimated GSM-based bit sequence may be selected by performing searches that start from trellis junctions determined by the decoding algorithm. The estimated bit sequences may be selected based on corresponding redundancy verification parameters. At least one physical constraint test may be performed on the selected estimated GSM-based bit sequences to select a decoded output GSM-based bit sequence. A multilayer decoding process may comprise a burst process and a frame process. Results from a first burst process may be utilized to generate a decoded GSM bit sequence in the frame process. The frame process may utilize redundancy information and physical constraints to improve the performance of a decoding algorithm.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: Systems and systems that protect data are provided. In one embodiment, a system may include, for example, a memory and a processor. The memory may store, for example, encrypted data. The processor may be coupled to the memory and may include, for example, a decryptor that decrypts the encrypted data. The decryptor may be adapted, for example, to variably bit roll the encrypted data, to fixedly bit shuffle the bit-rolled data, to add a first key to the bit-shuffled data and to process the added data with a second key.

Abstract: Aspects of a method and system for redundancy-based decoding in 8-PSK GSM systems are provided. A burst process may utilize a gradient search equalization operation to process a received 8-PSK modulated symbol sequence. A frame process may generate a redundancy-based decoded output bit sequence based on the burst process results. Iterative steps of the gradient search equalization operation may be utilized to converge to the burst process results. The redundancy-based decoded output bit sequence of the frame process may be fed back to a subsequent burst process. Results from the subsequent burst process may be utilized to generate a subsequent redundancy-based decoded output bit sequence by a subsequent frame process. The fed-back redundancy-based decoded output bit sequence may be combined with results from a Viterbi equalization operation within the subsequent burst process. Symbol-to-bits and bits-to-symbol conversions may be utilized during the burst process and during the subsequent burst process.

Abstract: Aspects of a method and system for use of true single phase clock (TSPC) logic for a high-speed multi-modulus divider in a phase locked loop (PLL) are provided. A fractional-N PLL synthesizer may comprise a divider that generates a divider signal from a VCO output reference signal. The divider may comprise at least one divider stage that utilizes true single phase clock (TSCP) logic D flip-flops. The first divider stage may operate at substantially the same frequency as that of the VCO signal. The divider may also re-synchronize the VCO signal and the divider signal by using at least two re-synchronization stages that utilize a TSCP logic D flip-flop and a stage for adjusting duty-duty cycle of the divider signal. The TSCP logic D flip-flops circuitry may be integrated with a two-input NAND gate or a three-input NAND gate to speed up the operation of the divider.

Abstract: Aspects of a double search user group selection scheme with range reduction for FDD multiuser MIMO downlink transmission with finite-rate channel state information feedback are provided. The method may comprise maximizing system capacity using feedback information for a plurality of signals in a frequency division duplex system to reduce a search range within which a group of signals having maximum channel gain are located. The feedback information may comprise quantized gain for the signals. Quantized channel direction for the signals within the reduced search range may be requested and received by the transmitter. One or two signals from the reduced search range that maximizes system capacity may be selected. The receivers associated with these signals may then be selected as the user group.

Abstract: A system and method for concealing input parameters that are being loaded into a device. In one embodiment, the system provides a transformed interface, in which a device into which the parameters are loaded contains a series of inverse transformation keys. The parameters to be concealed are transformed using a particular key, along with a transformed index value to indicate the particular key that must be used to inversely transform the parameter.

Abstract: Systems and methods that manage multiple stack environments are provided. In one example, a system may include, for example, a first protocol processing stack, a second protocol processing stack and a mapper. The mapper may be coupled to the first protocol processing stack and to the second protocol processing stack. A first port number may be associated with the first protocol processing stack and a second port number may be associated with the second protocol processing stack. The mapper may store a correspondence between the first port number and the second port number.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache. The present invention improves the of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: A system and method for enabling power applications over a single conductor pair. In one embodiment, data transformers are coupled to a single conductor pair using one or more direct current (DC) blocking elements that preserve an alternating current path. Power is injected onto the single conductor pair after the DC blocking elements and power is extracted from the single conductor pair before the DC blocking elements. Saturation of the data transformers by the injection of power onto the single pair is thereby prevented.

Abstract: Aspects of a method and system for generation of signals up to extremely high frequency using a delay block are provided. In this regard, a first signal may be delayed, via at least a portion of a plurality of delay elements and via a variable capacitance, to generate a second signal that is 90° out of phase relative to the first signal. Additionally, the first signal and second signal may be mixed to generate a third signal, wherein a frequency of the third signal is twice a frequency of said first signal. The portion of the delay elements utilized for delaying the signal may be controlled via one or more switching elements. In this regard, one of the plurality of delay elements may be selected to output the second signal. Moreover, the portion of the delay elements utilized for delaying the signal may be programmably controlled.

Abstract: A technique is provided for automatically adjusting the volume, or magnitude, of an audio signal. The technique includes calculating an average power associated with a segment of an input audio signal, determining whether the average power is greater than an estimated signal level associated with one or more previously-processed segments of the input audio signal and, depending on the determination, either calculating an updated estimated signal level by subtracting from the average power an attenuated difference between the estimated signal level and the average power or setting the updated estimated signal level to the average power. A gain to be applied to the segment of the input audio signal is then determined based on the updated estimated signal level and a target signal level for an output audio signal.