Abstract: The present invention is directed to a system for demultiplexing video signals that have been combined using a time division multiplexing approach. The system includes synchronizers, parsers, demultiplexers, and an input buffer. Each demultiplexer within the system includes a header detect module, a slot map module, a frame sync module and a packet accept module. The method includes the steps of receiving an input stream that contains data packets for more than one program channel that have been combined in which packet identification (PID) information is used and a time division multiplexing scheme, such as transport stream multiplexing format (TSMF) is used. The PID and slot location for each packet is analyzed. Based on the PID and slot location a packet is either accepted or rejected.

Abstract: A power status signal is received in an integrated circuit that indicates an inductive power status of an inductive power module and a power status of an alternative source. A power mode is selected based on the at least one power status signal. A power mode signal is generated based on the selected power mode. A power supply signal is generated and adjusted in response to the power mode signal.

Abstract: In integrated circuit includes a processing module that determines a selected one of the plurality of power modes based on a function being currently performed by at least one non-transceiver module of a host device, and generates a power mode signal based on the selected one of the plurality of power modes. An RF transmitter generates a transmit signal at a selected one of the plurality of operating power levels based on the power mode signal and that operates from at least one transmitter power supply signal generated and selected by a power management circuit in response to the power mode signal.

Abstract: A system and method for providing quality-of-service based network resource allocation and utilization in a dynamic network environment. For example, a wireless communication network may comprise a first system and a second system. The first system may provide a current service to a user at a current quality level. The first system and second system may establish a wireless communication link. At least one of the first and second systems may determine whether utilizing one or more resources of the second system will provide the current service to the user at a higher level of quality than the current quality level. One or more resources of the second system may be allocated for providing the current service to a user at a higher quality level. The allocated resources may be utilized to provide the current service to the user at a higher quality level than the current quality level.

Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

Abstract: A supervisory communications device, such as a headend device within a communications network, monitors and controls communications with a plurality of remote communications devices throughout a widely distributed network. The supervisory device allocates bandwidth on the upstream channels by sending MAP messages over its downstream channel. A highly integrated media access controller integrated circuit (MAC IC) operates within the headend to provide lower level processing on signals exchanged with the remote devices. The enhanced functionality of the MAC IC relieves the processing burden on the headend CPU and increases packet throughput. The enhanced functionality includes header suppression and expansion, DES encryption and decryption, fragment reassembly, concatenation, and DMA operations.

Abstract: A system and method for generating weight values based on maximum data rate for weighting elements included within signal weighting and combining arrangements used in various multi-antenna transmitter and receiver structures is disclosed herein. Weighting values for a given signal combining arrangement are set so as to maximize an output data rate of the applicable multi-antenna system in the presence of adaptive bit loading of the subcarriers of a transmitted signal. The disclosed techniques may be employed to maximize a data rate of a multi-antenna communication system by using adaptive bit loading and RF and baseband weighting schemes. In this case a search is conducted over various combinations of RF and baseband weights in order to find the weight combination which, when adaptive bit loading is also employed, maximizes the data rate.

Abstract: A system and method for providing upstream adaptive modulation. Burst parameters associated with a range of data interval usage codes (IUCs) are defined. Each of the data IUCs has a different modulation order and forward error correction (FEC). The SNR and codeword error rate for each satellite modem in the network are monitored. The data IUCs are dynamically assigned to different satellite modems within an upstream channel based on SNR and/or codeword error rate to enable each of the satellite modems in the upstream channel to achieve maximum bandwidth efficiency during upstream data transmissions. Bandwidth requests are received from the satellite modems and granted. The grant includes the assigned data IUC. The data bursts received in the upstream channel are each processed using the parameters from the assigned IUC for each of the satellite modems sending data in the upstream channel.

Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.

Abstract: An integrated circuit includes a first circuit and a first power supply line for powering the first circuit. A first intra-chip clock interface generates a first clock signal on the first power supply line. A second power supply line is coupled to the first power supply line and further powers the second circuit. A second intra-chip clock interface recovers the first clock signal from the second power supply line. The second circuit operates based on the first clock signal.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.

Abstract: Method and apparatus for processing satellite signals from a first satellite navigation system and a second satellite navigation system is described. In one example, at least one first pseudorange between a satellite signal receiver and at least one satellite of the first satellite navigation system is measured. At least one second pseudorange between the satellite signal receiver and at least one satellite of the second satellite navigation system is measured. A first difference between a first time reference frame of the first satellite navigation system and a time reference and a second difference between a second time reference frame of the second satellite navigation system and the time reference are obtained. The at least one first pseudorange and the at least one second pseudorange are combined using the first and second differences in time references.

Abstract: A receiver includes a plurality of RF receiver modules, a plurality of analog baseband sections, a plurality of analog to digital conversion sections, and a digital baseband processing module. The RF receiver modules convert inbound RF signals into a plurality of inbound analog signals. When the receiver is in a first mode, one of the plurality of analog baseband sections is active to adjust one of the plurality of inbound analog signals to produce an adjusted inbound analog signal; one of the plurality of analog to digital conversion sections converts the adjusted inbound analog signal into an inbound digital signal; and a portion of the digital baseband processing module is active to convert the inbound digital signal into inbound data.

Abstract: Aspects of a method and system are provided for error detection for improving data integrity in protocol offloading. Aspects of the invention may enable receiving a block of data having a modulo-based input error detection code and an error correction term appended thereto, calculating an output error detection code of the block, combining the input error detection code and the error correction term to produce a modified error detection code, and comparing the calculated error detection code to the modified error detection code so as to detect an error in the block. The error correction term may be equal to a binary difference between the input error detection code and the output error detection code. The input error detection code and the error correction term may be combined by applying an XOR operation.

Abstract: A supervisory communications node monitors and controls communications with a plurality of remote devices throughout a widely distributed network. A method is provided to convey and maintain information used to synchronize the packetization and burst operations within the network. During session setup, jitter constraints indirectly are used to explicitly communicate a synchronization timing reference. The timing reference is set at the beginning of a phase/period boundary used to service the session. In an embodiment, the announcement of the first grant is used as an explicit indication of the synchronization timing reference value. In another embodiment, the synchronization timing reference value is inferred if a remote device receives contiguous voice grants meeting certain conditions. In an embodiment implementing periodic scheduling, the actual arrival of the first grant is used to infer the synchronization timing reference value.

Abstract: Methods and associated systems provide secured data transmission over a data network. A security device provides security processing in the data path of a packet network. The device may include at least one network interface to send packets to and receive packets from a data network and at least one cryptographic engine for performing encryption, decryption and/or authentication operations. The device may be configured as an in-line security processor that processes packets that pass through the device as the packets are routed to/from the data network.

Abstract: A wireless power interface includes first coil, a plurality of coils, and a control module. Each of the plurality of coils has a different orientation with respect to at least one axis of a multi-dimensional axis system. The control module is coupled to enable at least one of the plurality of coils based on electro-magnetic coupling between the first coil and the at least one of the plurality of coils such that power is derived via the electro-magnetic coupling.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.

Abstract: According to an example embodiment, a wireless node may determine that a first reserved retransmission frame overlaps with a second reserved transmission frame and a second reserved retransmission frame and that the second reserved transmission frame overlaps with a first reserved transmission frame and the first reserved retransmission frame. The first reserved transmission frame and the first reserved retransmission frame may be reserved for wireless communication with a first master node, and the second reserved transmission frame and the second reserved retransmission frame are reserved for wireless communication with a second master node.