Abstract: A method to process a packet is described herein. The method comprises receiving a packet including a header and a payload. The header is parsed using a packet processor to determine type and priority of the packet. The header is then processed using a hardware acceleration block based on one or more of incoming bandwidth, priority and type of the packet. The custom hardware acceleration block generates header modification data that is sent to the packet processor. The header is modified using the packet processor, based on the header modification data, to generate a modified header. The modified header is appended to the payload and transmitted.

Abstract: Embodiments provide improved systems and methods of gain control and calibration for wireless transmitters. In particular, embodiments allow linear gain control over the entire transmitter gain control range, independent of temperature/process variations. Embodiments require very low power consumption compared to existing approaches. Embodiments may also be used for gain control calibration during production time, thereby substantially reducing production calibration time and cost.

Abstract: Various example embodiments are disclosed. According to an example embodiment, a switch may comprise an instruction decode stage and a lookup stage. The instruction decode stage may be configured to receive a bulk instruction identifying an action to perform on frame entries of the lookup stage, and in response to receiving the bulk instruction, send, to the lookup stage, at least first and second frame entry instructions, each of the first and second frame entry instructions identifying the action and identifying a unique frame entry in the lookup stage upon which to perform the action. The lookup stage may be configured to receive the first and second frame entry instructions from the instruction decode stage, and in response to receiving each of the first and second frame entry instructions, perform the identified action on the frame entry identified by the respective frame entry instruction.

Abstract: A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a transmission module. The phase interpolator is also coupled to a receiver interpolator control module and/or an external interpolator control module. When the system is operating in repeat mode, the transmitter phase interpolator receives a control signal from a receiver interpolator control module. The transmitter phase interpolator uses the signal to synchronize the transmission clock to the sampling clock. When the system is operating in test mode, a user defines a transmission data profile in an external interpolator control module. The external interpolator control module generates a control signal based on the profile. The transmitter phase interpolator uses the signal to generate a transmission clock that is used by the transmission module to generate a data stream having the desired profile.

Abstract: A transmitter capable of operating according to a first standard that does not interfere with a nearby frequency generator operating according to a second standard. The transmitter comprises an oscillator, a frequency divider, a mixer, and a filter. The oscillator is configured to output a first frequency that is outside of a frequency harmonic of the frequency generator. The frequency divider is coupled to the oscillator and divides the first frequency by a selective divide ratio to produce a second frequency. The mixer is configured to receive the first and second frequencies, which combines them to produce a mixed frequency. The filter is then used to filters the mixed frequency to obtain the higher portion of the mixed frequency. The divide ratio of the frequency divider is selected base on the desired output frequency of the transmitter such that a 2.4 GHz or 5 GHz ISM band frequency is achieved.

Abstract: A planer antenna structure includes a first planer antenna and a second planer antenna. The first planer antenna has a first axial orientation and a conductive antenna pattern on a first surface of a supporting substrate. The second planer antenna has a second axial orientation and the conductive antenna pattern on the first surface of the supporting substrate.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: Apparatus and method to process a pilot channel and a synchronization channel to obtain a combined noise estimate of the pilot channel and the synchronization channel that is synchronized to the pilot channel. The combined noise estimation is processed to determine a first noise component for a period when both the pilot channel and the synchronization channel are present. Then, the combined noise estimate is processed to determine a second noise component for a period when only the pilot channel is present. Next, the second noise component is subtracted from the first noise component to derive a noise estimation for the synchronization channel. The technique may be applied to the Common Pilot Channel (CPICH), and the Synchronization Channel (SCH) defined in a 3rd Generation Partnership Project standard specification.

Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.

Abstract: A system and method for dynamically reducing the precision of datapath modules within an FFT unit without adversely affecting the demodulation of an orthogonal frequency division multiplexing (OFDM) signal. An FFT unit is typically implemented in an OFDM receiver to separate sub-carriers within a received OFDM signal. In general, an FFT unit implemented within an OFDM receiver must be designed to operate with a precision high enough such that quantization noise, introduced within the FFT unit, does not dominate the overall maximum SNR requirement of the system. However, the SNR requirement for many OFDM receivers is dynamic and, as a result, OFDM receivers often have an instantaneous SNR requirement far below the required maximum. In these situations, it would be advantageous to reduce the precision of datapath modules within the FFT to conserve power, which is often limited in wireless devices.

Abstract: An integrated receiver with multiple, independently synchronized clock signals for multiple channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. An integrated circuit that services two satellite programs must generate and distribute corresponding time domain clocks to the various components of the integrated circuit. The transport block that receives one or more satellite signals from a demodulating block will extract program clock recover values from each signal being decoded and use these values to produce an error signal or control word that serves as an input to a clock generator. Based upon this input, the clock circuit will produce a corresponding time domain clock for each channel serviced by the integrated circuit. The output of the clock circuit is distributed to the various processing blocks within the integrated circuit that operate upon channel content received and processed by the transport block.

Abstract: At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.

Abstract: A network hub in a communication network that acts as a server to network clients to push, or transmit, information regarding the state of local and remote devices and networks. The information can be one, or more, status information, which information can be one or more predefined fields in a frame, which represents a packet of data. In one embodiment, it is desirable that the frame be a “legitimate” Ethernet-type frame. The status field can be a “push”-Type status field. The push operation can be a unicast, a multicast, or a broadcast, or a hybrid transmission. The hub can be a switch, repeater, a bridge, a router, a gateway, or a hybrid thereof. Also, the hub according to the present invention can be an OSI Layer 2 device, an OSI Layer 3 device, or a hybrid thereof. It is desirable that the hub be devoid of a microprocessor. As described herein, the hub may have plural ports, for example, four, eight, or more ports.

Abstract: An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and the diffusion area. A distance between the low doped well and the diffusion area determines a triggering voltage of the ESD device. A depletion region is formed between the low doped well and the substrate when a reverse bias voltage is applied to the ESD device. A current discharging path is formed between the first contact and the second contact when the depletion region comes in to contact with the diffusion area. The substrate is biased by a connection to the second contact. Alternatively, an additional diffusion area with the same dopant polarity, connected to a third contact, biases the substrate.

Abstract: Embodiments of the present invention enable a feedback-based VCO linearization technique. Embodiments include a frequency locked loop formed by feeding back a VCO's output into the VCO's input in negative phase by means of a frequency-to-voltage (F/V) converter. Embodiments enable constant VCO gain over a wide input tuning range and across PVT variations. Further, embodiments can be nested within a PLL, for example, with negligible area and power consumption overhead.

Abstract: A demodulator (10) converts television signals to video baseband signals and audio baseband signals including stereo signals representing a right channel signal value and a left channel signal value. A DSP (60) recursively finds a preferred coefficient value for a scaling that reduces stereo separation due to amplitude variation of the right and left channel signal values. The preferred coefficient value is thereafter used for scaling the right and left channel signal values.

Abstract: Aspects of a method and system for distribution of configuration information among access points (AP) in a WLAN across a distribution system (DS) are presented. An AP, performing in a role of an AP-configurator may configure another AP, performing in a role of AP-client. The AP-configurator may distribute configurator configuration information to the AP-client. A configured AP-client may adopt a role of AP-configurator to configure a subsequent AP-client. An AP-configurator, or configured AP-client may subsequently configure a client station. The AP-configurator or configured AP-client may distribute configuration information to the client station. The configuration information may be based on previously distributed configurator configuration information. The method may enable client stations to be configured based on common configuration information that may be derived from configurator configuration information that was distributed by an AP-configurator.

Abstract: In RF transceivers, a method and a system for a frequency feedback adjustment in digital receivers are provided. A DC offset may result from the difference in frequencies between an RF transmitter and an RF receiver. An adjustment of the receiver's frequency may be implemented after synchronization occurs and may be performed by, for example, utilizing a header portion of a packet communicated via a wireless interface. The adjustment may be performed when the frequency difference exceeds a threshold value. In another aspect, adjusting the frequency of the RF receiver may be performed by modifying and/or changing a phase locked loop (PLL) trimmer register. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.

Abstract: Embodiments of a scalable optical network unit (ONU) architecture for multi-dwelling units (MDUs) that has a low initial cost (or first port cost) and a low maintenance cost are provided herein. The ONU architecture is scalable in that a growing number of end users can share a single drop fiber that couples the ONU to a passive optical network. The ONU architecture utilizes a multiplexer module to allow the ONU to be daisy chained with one or more additional ONUs.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.