Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Abstract: Disclosed is a low mismatch semiconductor device that comprises a lightly doped channel region having a first conductivity type and a first dopant concentration in a semiconductor body, and a high-k metal gate stack including a gate metal layer formed over a high-k gate dielectric without having a dielectric cap on the high-k dielectric. The high-k metal gate stack being formed over the lightly doped channel region. The lightly doped channel region may be a P- or N-conductivity region, for example, and may be part of a corresponding P- or N-semiconductor substrate, or a P- or N-well formed in a substrate of the respectively opposite conductivity type. The disclosed semiconductor device, which may be an NMOS or PMOS analog device, for example, can be fabricated as part of an integrated circuit including one or more CMOS logic devices.

Abstract: Method and system encodes a signal according to a code rate that includes a ratio of uncoded bits to coded bits. An outer Reed-Solomon encoder encodes the signal into codewords. An interleaver converts the codewords into bits of frames for wireless transmission. An inner encoder executes a convolutional code to generate an encoded signal. The encoded signal is transmitted over a plurality of subcarriers associated with a wide bandwidth channel. The convolutional code is punctured and code states are added by the inner encoder to improve the code rate.

Abstract: Presented herein are method(s) and apparatus for demultiplexing, merging, and duplicating packetized elementary stream/program stream/elementary stream data. In one embodiment, there is presented a method for processing data. The method comprises receiving a bitstream wherein said bitstream comprises a plurality of streams; mapping the plurality of streams to a plurality of identifiers; packetizing the plurality of streams, thereby resulting in a plurality of packets, and wherein each packet further comprises: a portion of only one of the plurality of streams; and a particular one of the identifiers, wherein the particular one of the identifiers is mapped to the only one of the plurality of streams.

Abstract: Aspects of a method and system for reordered QRV-LST (layered space time) detection for efficient processing for multiple input multiple output (MIMO) communication systems are presented. The method may include receiving an ordered plurality of signals wherein each of the ordered plurality of received signals comprises information contained in an ordered plurality of spatial streams. Each spatial stream may comprise one or more frequency carriers, or tones. Information, or data, contained in a corresponding one of the ordered plurality of spatial streams may be detected. The order in which the information is detected may be determined for each individual frequency carrier.

Abstract: A radio frequency identification (RFID) decoding subsystem includes a pre-decode module and a decode module. The pre-decode module is coupled to process down-converted RFID signals into pre-decoded baseband data. The decode module is coupled to: enable a counting process based on the pre-decoded baseband data to produce a count resultant; and compare the count resultant with a threshold at a data bit interval to produce decoded RFID data.

Abstract: A radio frequency (RF) front-end includes a plurality of power amplifier modules and a plurality of impedance matching circuits. Each of the plurality of impedance matching circuits includes an input connection and an output connection, wherein outputs of the plurality of power amplifier modules are coupled to corresponding input connections of the plurality of impedance matching circuits to provide a desired loading of the plurality of power amplifier modules and wherein the output connections of the plurality of impedance matching circuits are coupled together to add power of the plurality of power amplifiers.

Abstract: A traffic prioritization system and method performs a coarse classification of upstream bursts at the physical interface of a wireless communications device. The wireless device monitors and controls communications with a plurality of remote wireless communications devices throughout a widely distributed network, including the Internet. The traffic prioritization system includes a burst receiver that receives and sends the upstream bursts to a classifier. At an appropriate time, the classifier receives the upstream bursts and queries a priority lookup table (LUT) to determine a priority classification. The priority classification is used to separate the bursts into two or more priority levels. The higher priority level is used to designate services having a low tolerance for delay, such as telephony. Upon classification, the upstream bursts are forwarded to one of several priority queues. Each priority queue corresponds to at least one priority level.

Abstract: Classifier for communication device. A communication device includes a classifier and a number of PHY (physical layer) receivers communicatively coupled thereto that enable the communication device to process various received signal types. Each of the PHY receivers is operable to perform pre-processing of a received frame (or packet) of data and to calculate a confidence level indicating whether the received frame is intended for that particular PHY receiver; this pre-processing does not involve processing (e.g., demodulation and/or decoding) of the received frame. Those PHY receivers having sufficiently high confidence levels assert claims to the classifier for the received frame. The classifier is operable to arbitrate between competing claims by 2 or more PHY receivers and to ensure that the received frame is provided to the PHY receiver for which it is intended.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: Provided are a method and system for determining system time in a satellite based cable data communication system. The system includes a satellite modem termination system configured to transmit data frames to a receiver in a predetermined symbol rate. Each frame includes a corresponding number of symbols and has a time stamp (i) indicative of the frame's time of transmission and (ii) positioned within the frame at a location common to all of the frames. The method includes receiving at least two consecutively transmitted data frames within the receiver and registering the time stamp of the first received data frame within the receiver to produce a first time stamp. Also, the time stamp of the second received data frame is registered within the receiver to produce a second time stamp. The time of transmission of the second transmitted data frame is updated, wherein the updating is a function of the first time stamp, the second time stamp, the corresponding number of symbols, and the symbol rate.

Abstract: In a video processing system, a method and system for joint broadcast receiving and cellular communication via a mobile terminal or device with UMTS as an integration channel are provided. Broadcast information may be received at a mobile terminal via a VHF/UHF broadcast communication path. Cellular information, comprising voice and data, may be received at the mobile terminal from a bidirectional cellular communication path. Broadcast information may be received at the mobile terminal via the bidirectional cellular communication path. The information may be received from a service provider. Uplink cellular related information may be transmitted via an uplink path of the bidirectional cellular communication path. The mobile terminal may comprise a common interface that facilitates communication between at least one cellular processor that processes the cellular information and a broadcast processor that processes the broadcast information.

Abstract: A hardware packets reassembly apparatus and method includes an ingress unit receiving and parsing a data packet, recognizing fragments corresponding to the data packet, and outputting control information of the fragments. An en-queue unit stores the control information of each fragment, links each related fragment based on the control information, and enqueues the data packet when all fragments are available corresponding to the data packet, wherein the data packet is enqueued only when all of the fragments corresponding to the data packet are available in a sequential order. A dequeue unit dequeues the data packet from a packet descriptor, and scheduling the data packet based on a corresponding class of service. An egress unit assembles all fragments corresponding to the data packet into a full packet and outputting the assembled data packet from an output port.

Abstract: A system and method for providing access to a video display for multiple devices. Various aspects of the present invention may comprise receiving, at a video display system, a first video data signal through a first data communication interface and a second video data signal through a second data communication interface. A processor module may process the first and second video data signals to generate video information of first and second display windows in a composite display. For example, the processor module may transform and translate video information to fit display windows. The processor module may, for example, generate an output video signal comprising information of the first window and information of the second window. Such a signal may, for example, be utilized to drive an output display showing the first and second windows. Various aspects may also provide method steps and apparatus for controlling aspects of the displayed windows.

Abstract: Methods and systems for processing signals in a receiver are disclosed herein and may comprise receiving WCDMA signals via M receive antennas, tracking a plurality of received clusters within the received WCDMA signals, and estimating a complex phase and amplitude of a portion of each of the received clusters. A single cluster may comprise an aggregate of received WCDMA signal paths and (M-1) phase shifters may be utilized for the estimating of the complex phase. Complex waveforms, comprising in-phase (I) and quadrature (Q) components for the received clusters within the received WCDMA signals, may be processed. The processed complex waveforms comprising the in-phase and quadrature components may be filtered to a WCDMA baseband bandwidth. A phase and/or amplitude for at least one of the received WCDMA signals may be adjusted utilizing the estimated complex phase and amplitude. The phase and/or amplitude may be adjusted continuously and/or at discrete intervals.

Abstract: A method for generating a preamble of a frame for a multiple input multiple output (MIMO) wireless communication begins by, for each transmit antenna of the MIMO wireless communication, generating a carrier detect field, wherein, from transmit antenna to transmit antenna, the carrier detect field is cyclically shifted. The method continues by, for a first grouping of the transmit antennas of the MIMO wireless communication: generating a first guard interval following the carrier detect field; and generating at least one channel sounding field, wherein, from transmit antenna to transmit antenna in the first grouping, the at least one channel sounding field is cyclically shifted, and wherein the at least one channel sounding field follows the first guard interval.

Abstract: Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.

Abstract: A semiconductor memory, such as an SRAM, is described that accommodates smaller read/write accesses in one mode of operation and larger read/write accesses in a second mode of operation, wherein power is conserved during the smaller accesses. Methods of using such a semiconductor memory are also described.

Abstract: Multiple channel synchronized clock generation scheme. A novel approach is presented herein in which synchronized clock signals are generated that can be used in parallel processing of deserialized signals. When a serial input signal is received, it can be deserialized into a plurality of parallel signals, and each of these parallel signals can be processed at a frequency that is lower than the frequency of the serial signal. Overall, the frequency at which all of the parallel signals are processed can be the same or substantially close to the frequency of the serial signal, so that throughput within a communication system is not compromised or undesirably reduced. This novel approach is operable to perform independent adjustment of the operational parameters within an apparatus that is operable to perform multiple channel synchronized clock generation (e.g., phase rotation and/or division of signals within each of the individual channels can be adjusted independently).

Abstract: Systems and methods for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip are disclosed. The systems and methods include the use of a breakpoint mechanism, and modification of parameters at runtime, with the breakpoint mechanism being additionally used in debugging, in order to provide some of the looping functionality.