Abstract: A method to provide a low-power clock signal or a low-noise clock signal is described herein. It is determined whether a low-power mode or a low-noise mode is in use. A voltage reference input of a low-dropout voltage regulator (LDO) is switched to a low-power voltage reference for low-power mode and to a low-noise voltage reference for low-noise mode. The LDO provides a constant voltage output to a crystal oscillator. A clock signal is generated using the crystal oscillator. The clock signal is limited using a low-power limiter to generate a low-power output clock signal and/or is limited using a low-noise limiter to generate a low-noise clock signal. The low-power output clock signal or the low-noise output clock signal is selected using a mux.

Abstract: Systems and methods are described for managing bit errors present in a series of encoded bits representative of a portion of an audio signal, wherein the series of encoded bits is received over a communication link in an audio communications system. At least one characteristic of a portion of a received modulated carrier signal that is demodulated to produce the series of encoded bits is determined. A number of bit errors present in the series of encoded bits is then determined based on the at least one characteristic. Based on the estimated number of bit errors, one of a plurality of methods for producing a series of digital audio samples representative of the portion of the audio signal is selectively performed. The series of digital audio samples produced by the selected method is then converted into a form suitable for playback to a user.

Abstract: An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.

Abstract: An integrated circuit (IC) includes a baseband processing module and a radio frequency (RF) section. The baseband processing module is coupled to convert outbound data into amplitude modulation information and phase modulation information when the IC is in a cellular data mode and to convert an outbound radio frequency identification (RFID) signal into RFID amplitude modulation information when the IC is in an RFID mode. The RF section is coupled to generate an outbound RF data signal in accordance with the amplitude modulation information and the phase modulation information when the IC is in the cellular data mode and to generate an outbound RF RFID signal in accordance with the RFID amplitude information when the IC is in the RFID mode.

Abstract: A method of transmitting data in a cable modem system includes the steps of encoding the data using forward error correction. The data is then encoded with Turbo encoding. The data is then sent to a modulation scheme. The data is then transmitted over a cable channel. The data is then demodulated. The data is then decoded using a Turbo decoder. An inverse of the forward error correction is then applied to the data.

Abstract: According to one exemplary embodiment, a differential varactor circuit for a voltage controlled oscillator having two differential outputs includes a first varactor having first and second terminals and a second varactor having first and second terminals. In the differential varactor circuit, each of the first and second terminals of the first varactor and each of the first and second terminals of the second varactor are coupled to one of the two differential outputs of the voltage controlled oscillator, thereby allowing a size of each of the first and second varactors to be reduced so as to increase varactor quality factor. Each of the first and second terminals of the first varactor can be coupled to one of the two differential outputs by a capacitor, and each of the first and second terminals of the second varactor can be coupled to one of the two differential outputs by a capacitor.

Abstract: An LED driver circuit is disclosed that can drive a plurality of LED strings that are arranged in parallel, each LED string having a plurality of component LEDs that are series-connected. The LED strings can be the same type of LEDs in each string, or have different types of LEDs from one string to another. The LED driver includes a voltage control loop that dynamically regulates the output voltage across the parallel arrangement of LED strings. The output voltage is dynamically adjusted to accommodate the LED string with the largest operational voltage drop. This enables LED displays to constructed using different types of LEDs strings, but still supply the LED strings in a power efficient manner. Further, each LED string also includes its own individual current regulation loop so that the current, and therefore brightness, of each LED string can be individually adjusted.

Abstract: An antenna system includes a wired communications interface, an antenna, and antenna system control circuitry. The wired communications interface is operable to couple to a serviced host device and includes a control interface and an antenna interface. The antenna couples to the antenna interface and has configurable antenna characteristics. The antenna system control circuitry couples to the control interface and to the antenna and is operable to communicate the configurable antenna characteristics to the host device and to configure the antenna based upon communication with the host device. In other constructs the antenna may not be configurable and the antenna characteristics communicated are fixed. The antenna system may further include Radio Frequency (RF) transmit circuitry and/or RF transmit circuitry. Such RF transmit circuitry and RF receive circuitry may be configurable or fixed in its operations.

Abstract: An integrated circuit radio receiver includes radio frequency (“RF”) front-end circuitry to receive a wireless signal and to produce digital data. The integrated circuit radio receiver includes a baseband processor is operable to process the digital data, in which the baseband processor is operable to produce a format designation based on the digital data. The baseband processor includes a plurality of digital filtering logic in which each of the digital filtering logic includes a level of digital filtering. The baseband processor further includes logic operable to select between each digital filtering logic of the plurality of digital filtering logic based upon the format designation, and to process the digital data with the selected level of digital filtering.

Abstract: A radio transceiver device includes circuitry for radiating electromagnetic signals at a very high radio frequency both through space, as well as through wave guides that are formed within a substrate material. In one embodiment, the substrate comprises a dielectric substrate formed within a board, for example, a printed circuit board. In another embodiment of the invention, the wave guide is formed within a die of an integrated circuit radio transceiver. A plurality of transceivers with different functionality is defined. Substrate transceivers are operable to transmit through the wave guides, while local transceivers are operable to produce very short range wireless transmissions through space. A third and final transceiver is a typical wireless transceiver for communication with remote (non-local to the device) transceivers.

Abstract: A navigation system includes a Global Positioning System (GPS) enabled wireless phone and a GPS navigation system. The GPS enabled wireless phone includes a GPS receiver, a communications interface, and processing circuitry coupled to the GPS receiver and to the communications interface. The GPS navigation system includes a GPS receiver, a communications interface operable to communicatively couple to the communications interface of the GPS enabled wireless phone, and processing circuitry coupled to the GPS receiver and to the communications interface. The processing circuitry of the GPS navigation system is operable to establish device pairing with the GPS enabled wireless phone and to exchange GPS information and other information with the GPS enabled wireless phone via the secure link.

Abstract: A method and apparatus is disclosed to compensate for interference and/or distortion impressed onto a transmitted communications signal in the presence of one or more time-varying conditions. A communications receiver includes a noise analyzer to characterize the composition of the interference and/or distortion impressed onto a transmitted communications signal in the presence of one or more time-varying conditions. The noise analyzer may provide a selection signal indicating the composition of the interference and/or distortion impressed onto a transmitted communications signal in the presence of one or more time-varying conditions to be used by the communications receiver. In an exemplary embodiment, the communications receiver selects at least one set of filter coefficients to compensate for the interference and/or distortion impressed onto a transmitted communications signal in the presence of a particular time-varying interference and/or distortion condition.

Abstract: Systems and methods of coding progressive content with isolated fields for conversion to interlaced display are provided. Some systems and methods may find use in, for example, digital video compression systems and methods. Film material may be encoded as video material with an intended field polarity and an explicit 3:2 pull-down operation for interlaced display (e.g., a 30-frames-per-second display).

Abstract: A method for load balancing in a link aggregation environment, wherein the method includes the steps of determining if a packet flow in a network switch exceeds a predetermined threshold. Then the method includes the step of determining if the packet flow is a candidate for link switching from a first link to a second link if the packet flow exceeds the predetermined threshold. Additionally, the method includes switching the packet flow from the first link to the second link if the packet flow is determined to be a candidate for link switching. Additionally, a method for load balancing in a link aggregation environment including the steps of determining a length of a first frame and a length of a second frame entering the link aggregation environment. Thereafter, determining a flow rate of the first frame and the second frame entering the link aggregation environment.

Abstract: Methods and systems for input/output pads in a mobile multimedia processor are disclosed and may include receiving data from a host device in an integrated circuit having at least one contact pad and generating at least one control signal that controls the contact pads. The received data may be processed by the MMP based on the generated at least one control signal, or may be passed through the MMP in a bypass mode based on the control signal, thereby allowing the received data to pass through the MMP without processing to an external memory via the at least one contact pad, thereby sharing the external memory with the host device. The data may be transferred to external memory coupled to a contact pad on the MMP when the received data is to be passed through the MMP. The received data may be stored temporarily before transfer to an external device.

Abstract: Aspects of a method and system for redundancy-based decoding of voice content in a wireless local area network (WLAN) system are provided. A WLAN receiver may determine whether a decoded portion of a received packet comprises voice content and may select a redundancy-based decoder to decode a remaining portion of the packet when voice content is detected. The redundancy-based decoder may be a Viterbi decoder. The redundancy-based decoder may be selected to decode a determined number of subsequent packets or to decode subsequent packets for a determined amount of time. After decoding the remaining portion of the packet and any subsequent packets, the WLAN receiver may select a standard Viterbi decoder to decode additional received packets. The WLAN receiver may generate at least one signal to select the redundancy-based decoder and the standard Viterbi decoder.

Abstract: A radio transmitter integrated circuit includes a photodiode array circuit, a digital conversion module, a transmit baseband processing module, an analog conversion module, an up-conversion module, and a power amplifier circuit. The photodiode array circuit is coupled to convert received light into electrical image signals. The digital conversion module is coupled to convert the electrical image signals into digital image signals. The transmit baseband processing module is coupled to convert the digital image signals into digital transmit baseband or low IF signals. The analog conversion module, the up-conversion module, and the power amplifier circuit are coupled to convert the digital transmit baseband or low IF signals into transmit radio frequency (RF) signals.

Abstract: A method and apparatus for tunneling protocols are described. In one embodiment, the method comprises broadcasting a message at a repeater to one or more members in a network including a switch, the broadcasted message indicating that the repeater is entering the network, receiving VLAN (virtual local area network) configuration information from the switch in response to the broadcast message, and communicating with the switch using the VLAN configuration information in subsequent communications.

Abstract: An embodiment of the present invention provides a system for implementing a Reed-Solomon computation of parity bytes of a codeword, including an accumulator and a logic circuit. The accumulator is configured to hold a plurality of bits. In an embodiment, each bit held in the accumulator initially corresponds to a bit associated with a data byte of the codeword. In another embodiment, each bit held in the accumulator initially correspond to a fixed value. The logic circuit is configured to iteratively compute a new bit for each bit held in the accumulator. After a last iteration of the computation, the bits held in the accumulator correspond to the parity bytes, wherein for each bit held in the accumulator each iteration of the computation comprises computing an exclusive-OR of a fixed subset of bits held in the accumulator. In an embodiment, the exclusive-OR is computed for the fixed subset of bits held in the accumulator and an input bit of the codeword.

Abstract: A modular wireless headset to support voice communications that includes a wireless microphone, a wireless earpiece, and a tether. Both the wireless microphone and wireless earpiece have receptacles operable to receive the tether and one or both of the wireless microphone and wireless earpiece have portable power supplies operable to power the containing module. The tether allows the wireless earpiece or wireless microphone to provide power to operate and/or recharge the microphone or wireless earpiece when the wireless microphone or wireless earpiece is coupled with the tether.