Abstract: Embodiments of a SAW-less RF receiver front-end that includes a frequency translated notch filter (FTNF) are presented. An FTNF includes a passive mixer and a baseband impedance. The baseband impedance includes capacitors that form a low-Q band-stop filter. The passive mixer is configured to translate the baseband impedance to a higher frequency. The translated baseband impedance forms a high-Q notch filter and is presented at the input of the FTNF. The FTNF can be fully integrated in CMOS IC technology (or others, e.g., Bipolar, BiCMOS, and SiGe) and applied in wireless receiver systems including EDGE/GSM, Wideband Code Division Multiple Access (WCDMA), Bluetooth, and wireless LANs (e.g., IEEE 802.11). In addition, embodiments of a generalized FTNF for wideband applications are presented.

Abstract: Embodiments of the present invention provide constant output DC biasing circuits. Embodiments employ an open loop scheme, instead of a closed loop scheme as used in conventional circuits. In addition, embodiments generate a DC bias voltage that is independent of temperature, process, and power supply variations. Further, embodiments require low amounts of power and silicon.

Abstract: A circuit includes a first wireless interface circuit that transceives packetized data between a host module and a first external device in accordance with a first wireless communication protocol. A second wireless interface circuit transceives packetized data between the host module and a second external device in accordance with a second wireless communication protocol. The second wireless interface circuit includes at least one module that is shared with first wireless interface circuit. The first wireless interface circuit and the second wireless interface circuit operate in accordance with a wireless interface schedule that includes a first time interval where the first wireless interface device and the second wireless interface device contemporaneously use the at least one module.

Abstract: Increased cable length Power over Ethernet (PoE) systems are provided. Embodiments can be designed for compliance with IEEE 802.3af, IEEE 802.3at, or legacy PoE standards. Embodiments include PSE and PD designs enabled for increased length PoE. Embodiments include example modifications of IEEE 802.3af PSE system rules, including example modifications of PSE port voltage ranges to support IEEE 802.3af compliant PDs across increased cable lengths. Embodiments include example modifications of IEEE 802.3af PD system rules, including example modifications of PD port voltage ranges to enable current IEEE compliant PSEs to support increased cable length PoE. Embodiments include PDs having increased voltage process and/or added voltage protection circuitry to support increased length PoE. Modifications of PSE system rules and PD system rules can be performed independently of each others, so that modified PSEs can be made to work with existing PDs, or vice versa.

Abstract: A method, apparatus, and system for automatically sharing data resources between Bluetooth devices. A Bluetooth device is paired with a “trusted” Bluetooth device. When paired devices are found, the Bluetooth device automatically allows the other device to present a virtual representation of data that is shared. The shared data can be selectively downloaded for use by the other device as long as the devices are in proximity. In an alternate embodiment, the devices may share pairing information with a network, so that the same shared resource can be made available at a large number of access points but specifically only for one paired, trusted device.

Abstract: Embodiments of the present invention provide a system that identifies an even delimiter in a forward error correction (FEC)-coded Ethernet frame. The system receives an FEC-coded Ethernet frame that includes the even delimiter, which is a predetermined sequence that separates a conventional Ethernet frame and FEC parity bits in the FEC-coded Ethernet frame. Next, the system scans a bit stream of the FEC-coded Ethernet frame. Then, the system determines a first Hamming distance between a first consecutive set of frame bits in the bit stream and the even delimiter. The system also determines a second Hamming distance between a second consecutive set of frame bits in the bit stream and the even delimiter. Both the first and second Hamming distances are shorter than a predefined value. The system subsequently selects one of the first and second sets of frame bits having the shorter Hamming distance as the even delimiter.

Abstract: Embodiments of a SAW-less RF receiver front-end that includes a frequency translated notch filter (FTNF) are presented. An FTNF includes a passive mixer and a baseband impedance. The baseband impedance includes capacitors that form a low-Q band-stop filter. The passive mixer is configured to translate the baseband impedance to a higher frequency. The translated baseband impedance forms a high-Q notch filter and is presented at the input of the FTNF. In an embodiment, the capacitors are implemented using MOS capacitors. In another embodiment, the capacitors are partially formed from MOS capacitors and fringe capacitors. The FTNF can be fully integrated in CMOS IC technology (or others, e.g., Bipolar, BiCMOS, and SiGe) and applied in wireless receiver systems including EDGE/GSM, Wideband Code Division Multiple Access (WCDMA), Bluetooth, and wireless LANs (e.g., IEEE 802.11).

Abstract: Example methods and apparatus for hierarchical bandwidth management are disclosed. An example method includes, receiving a data packet included in a first data traffic flow having a first rate of traffic. The example method further includes marking the data packet with a first marker type if the first rate of traffic is less than or equal to a first threshold, otherwise marking the data packet with a second marker type. The example method also includes combining the first data traffic flow with a second data traffic flow having a second rate of traffic to produce a third data traffic flow having a third rate of traffic. The example method still further includes, if the data packet is marked with the first marker type, forwarding the data packet in the third data flow.

Abstract: A method for processing video image data including a plurality of different image data types begins by providing tasks to be performed on each different image data type. The image data is divided into a plurality of groups based on the image data type. A set of arithmetic operations required to accomplish the tasks provided for the corresponding image data type is determined. Each arithmetic operation is assigned to one of a plurality of commonly used arithmetic units which performs the arithmetic operation, whereby each image data type is transformed in accordance with the corresponding provided tasks. The transformed image data of each group is combined, completing the processing.

Abstract: Described herein is a rate controller in a video system. The rate controller estimates a bit count, and controls three adaptive rate control loops. The master rate control loop is in control of the quantizer. The slave rate control loops control coarse motion estimation and fine motion estimation.

Abstract: In a RF communications system, aspects for single weight antenna system for HSDPA may comprise receiving HSDPA signals via a plurality of receive antennas and individually adjusting a phase of a portion of the received HSDPA signals via a single weight. The phase adjusted portion of the received HSDPA signals may be combined with at least one of the received HSDPA signals to generate combined HSDPA signals. At least one control signal may control the adjusting of the phase of the received HSDPA signals. Discrete phases may be communicated to adjust the phase of the portion of the received HSDPA signals, where the plurality of the discrete phases may range from zero radians to substantially 2? radians. Phase shift channel estimates may be generated during the identified time to determine the discrete phase. A desired phase may be generated from the phase shift channel estimates, and the single weight may be generated from the desired phase.

Abstract: The present invention is directed to a line address computer for calculating the starting line addresses for lines of a decoded frame. The starting addresses for a display frame are provided to the line address computer by a host processor. The line address computer determines the starting line addresses for subsequent lines by appropriately incrementing the line addresses of previous lines.

Abstract: Aspects of a method and system for managing an energy efficient network utilizing Audio Video Bridging are provided. In this regard, an Audio Video Bridging timeslot may be designated for handling an energy efficient networking (EEN) transaction and the EEN transaction may be performed during the designated timeslot. Exemplary EEN transactions comprise scheduling a data rate transition, transitioning to a different data rate, training a link partner, and exchanging training related information. It may be determined whether the timeslot may be reserved for conveying an AVB stream prior to designating the time slot for an EEN transaction. In instances that the timeslot may be unreserved, the timeslot may be reserved for EEN transaction(s). Information exchanged during the designated timeslot may enable scheduling a data rate transition and/or training on a network link. In this regard, a subsequent timeslot may be designated for the data rate transition and/or the training.

Abstract: The present invention relates to a system and method adapted to optimize power consumption in a communication system used in a Gigabit Ethernet environment. The method comprises determining at least one power mode of a host from a plurality of possible host power modes. The method further comprises selecting at least one network interface power management state from a plurality of possible network interface power management states based, at least in part, on the determined power mode.

Abstract: Certain embodiments of an extreme power down mode for extreme power savings when no network presence is detected may comprise disabling at least one device driver for at least one hardware device in a network adapter chip. The device driver may be disabled prior to disabling the hardware device upon starting a power reduction mode for the network adapter chip. The device driver for the hardware device on the network adapter chip may be enabled after enabling the hardware device upon ending a power reduction mode for the network adapter chip. The hardware device may be disabled by reducing power to it. Similarly, power may be provided to the hardware device to enable it. The network adapter chip may be reset to enable the hardware device upon providing power to the hardware device so that the hardware device may be at a known state.

Abstract: Systems and methods for interleaver and deinterleaver memory partitioning optimize data rate and error correction. Optimized memory allocation is important in systems that support bi-directional communication over multiple data paths. By using path-specific information such as impulse noise protection and data rate, memory may be dynamically partitioned to optimize the capacity in individual data paths.

Abstract: Methods and systems for processing signals via directional couplers embedded in an integrated circuit package are disclosed and may include generating via a directional coupler, one or more output RF signals that may be proportional to a received RF signal. The directional coupler may be integrated in a multi-layer package. The generated RF signal may be processed by an integrated circuit electrically coupled to the multi-layer package. The directional coupler may include quarter wavelength transmission lines, which may include microstrip or coplanar structures. The directional coupler may be electrically coupled to one or more variable capacitances in the integrated circuit. The variable capacitance may include CMOS devices in the integrated circuit. The directional coupler may include discrete devices, which may be surface mount devices coupled to the multi-layer package or may be devices integrated in the integrated circuit. The integrated circuit may be flip-chip bonded to the multi-layer package.

Abstract: A wireless access point and multiple wireless terminals exchange utilization, status, mobility and reception characteristics. Each wireless terminal generates reception characteristics based on transmissions received from the wireless access point and from other devices in the network. In one operating mode, the characteristics gathered by the wireless devices are forwarded to the wireless access point, and, based on all received characteristics, the wireless access point selects its own transmission power for different types of the transmission. In another mode, all characteristics are exchanged between every wireless terminal and the access point so that each can independently or cooperatively make transmission power control decisions. In a further mode, the wireless access point adjusts protocol parameters based on an assessment of the characteristics received from the client devices, to detect an event such as a hidden terminal condition.

Abstract: On-chip MOS circuitry couples a communication path between an output stage amplifier and an output port and disables a circuit path between an input amplifier and the output port by creating a high impedance circuit during transmit operations. Alternatively, the circuitry opens the transmit circuit path with an isolated MOSFET and enables the second circuit path by creating an impedance matched circuit. The switch is formed within an isolated region to allow it to float with a signal to avoid breakdown. This floating MOS switch can be used for a variety of other applications in addition to its use as a transmit/receive switch even though formed on the same die as the communication circuitry.

Abstract: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed by a Non-ISI Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Non-ISI Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Non-ISI Meta-Viterbi detector receives an output generated from a symbol detector and processes the received output using a trellis having 2t states. In a representative embodiment, the overall implementation complexity of the Non-ISI Meta-Viterbi detector is bounded by no more than ?+(?)2t2t operations, wherein t represents the number of parity bits used in a codeword and ? represents codeword length in bits.