Abstract: A digital electronic device supports program transmission to a recipient device via the Internet. A frame adapter decodes incoming IP program packets and re-encodes resulting program signals adaptively to optimally suit the recipient device based upon configuration data of the recipient device. The frame adapter receives feedback from the recipient device, which may include a characterization of a communication path between the digital electronic device and the recipient device. The frame adapter utilizes the configuration information to generate the optimal video frame stream that is transmitted to the recipient device. The compression itself involves producing optimal number of base and predicted video frames.

Abstract: Various example embodiments are disclosed. According to an example embodiment, a network device may include a memory management unit. The memory management unit may be configured to populate a count field based on a number of equal cost paths for each Internet Protocol (IP) route for a packet, randomly choose one of the equal cost paths for the packet, and send the packet out of the network device, the packet including route information for the chosen equal cost path.

Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.

Abstract: A servo writer includes a servo data generation module that generates servo data corresponding to a plurality of servo wedges and a plurality of tracks of a disk, the servo data including track identification data that is repetition coded. A servo write module writes the servo data on the disk.

Abstract: An integrated circuit radio transceiver and method therefor includes capacitive loop filter with selectable capacitive elements that are operable to adjust a signal level provided to a voltage controlled oscillator to control a frequency of an output signal of the oscillator. A plurality of switches are controlled by logic to define a discharge mode, a charge mode and charge sharing mode in which a plurality of capacitive elements share charge while generating the input voltage to the oscillator.

Abstract: A digital electronic device includes a time shifter/tone adapter that eliminates unwanted audio effects at recipient device, that includes stutter and loss of audio synchronization, as a result of video quality adaptation (the video quality adapter varies frame rate, pixel and color resolutions without having a discernable difference in picture quality, that is, drops many frames in every frame set). The tone adaptation involves gradual frequency shifting, that is, gradual up shifting until synchronization with video is obtained (time shifting), then gradual down shifting. The recipient device (or a set top box) may contain a time shifter/tone adapter that eliminates unwanted audio effects at the recipient devices that may include stutter and loss of audio synchronization, as a result of loss of packets in channel.

Abstract: A method and related computer program product of preventing write corruption in a redundant array in a computer system, comprising detecting a write failure from a calling application to at least one disk of the redundant array, writing failure information to non-volatile storage; returning an I/O error to the calling application; reading the failure information from the non-volatile storage during the next system reboot; and reconfiguring the array to eliminate the failed disk.

Abstract: In a network having a first node and a second node, a method of verifying a lane routing between the first node and the second node. The first node and the second node operate according to a protocol in which: (1) a character is converted to code groups, (2) each code group has a corresponding lane, and (3) the code groups are communicated across the lanes in a parallel manner. A first set of code groups is transmitted from the first node. Preferably, the first set of code groups is different from a set of code groups predefined by the protocol. A second set of code groups is received at the second node. The second set of code groups corresponds to the first set of code groups. A determination is made whether the second set of code groups matches the first set of code groups. An identity of the first set of code groups can be preprogrammed within the second node. Preferably, the first set of code groups has a different code group in each lane.

Abstract: Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d in which d is an integer and a code generator coupled to the FIFO memory. The code generator may provide, for example, a first code sequence of length 2d. The first code sequence may have a circular property and a Hamming length of one for any two consecutive codes of the first code sequence. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.

Abstract: Position based WPAN (Wireless Personal Area Network) management. Based on either the relative position or the specific location of devices within a WPAN, communication between the various devices is managed by grouping the devices into two or more groups. In addition, the communication between theses various devices may be governed by profiles assigned to the groups (or even the actual individual devices) that are assigned based on their locations within the WPAN. The relative locations of the devices may be made using ranging that is performed by transmitting UWB (Ultra Wide Band) pulses between the various devices within the WPAN. Alternatively, each device may include GPS (Global Positioning System) functionality and information corresponding to the specific locations of the devices may be communicated between the devices, and that information may be used to group devices user and/or assign profiles to govern the communication to and from the devices.

Abstract: A servo writer includes a servo data generation module that generates servo data corresponding to a plurality of servo wedges and a plurality of tracks of a disk, the servo data including burst data that is repetition coded. A servo write module writes the servo data on the disk.

Abstract: Aspects of a method and system for an RF front-end calibration scheme using signals from a fractional-N frequency synthesized and received signal strength indicator (RSSI) are provided. A frequency synthesizer within a wireless receiver may generate a signal for dynamically modifying a gain in an integrated low-noise amplifier (LNA) for each selected receiver channel. The frequency-synthesized signals may be applied to at least one tunable load communicatively coupled to the LNA. The tunable load may be an input load or an output load. The signal generated by the frequency synthesizer may be sequentially applied to the input load and the output load. A logarithmic amplifier may generate an RSSI signal from the LNA output during the calibration process. The RSSI signal may be utilized for controlling a tunable load coupled to the LNA and optimize the tuning of the LNA in a desired channel by adjusting the tunable load.

Abstract: A low power integrated circuit (IC) includes a power supply module, first circuitry, and second circuitry. The power supply module is coupled to receive a power source signal from a source external to the low power IC, derive an electromagnetic signal from the power source signal, and convert the electromagnetic signal into a supply voltage. The first circuitry is coupled to produce a first resultant from a first stimulus, wherein the first circuitry is powered via the supply voltage. The second circuitry is coupled to produce a second resultant from a second stimulus, wherein the second circuitry via powered by the supply voltage.

Abstract: Methods and associated systems for processing data are disclosed. A hashing function sequentially processes a hash key to generate a hash value. A policy management system processes packets according to defined policies.

Abstract: A power amplifier circuit including a first transistor, a second transistor, and a power control circuit. The first transistor includes a first input and a first output. The second transistor includes a second input coupled in series with the first output of the first transistor. The input circuit is coupled to the second input of the second transistor. The control circuit includes a time delay circuit and a variable source.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.

Abstract: A self servo writing disk controller detects a plurality of spiral sync marks and a plurality of spiral bursts corresponding to one of a plurality of servo spirals from a read signal from the read/write head. A timing reference signal is generated based on timing of at least one of the plurality of the spiral sync marks. A position error signal is generated based on timing of at least one of the plurality of spiral sync marks and a magnitude of at least one of a plurality of spiral bursts. The timing reference signal and the position error signal are used by the disk drive for timing and positioning in self writing initial servo wedges to the disk.

Abstract: A token-based receiver diversity processing is described. In one embodiment, a receiver diversity comprises repeaters receiving wirelessly transmitted packets from a mobile station, and one of the repeaters forwarding packets of the wirelessly transmitted packets to a switch if the one repeater is currently assigned to forward packets from the mobile station based on an indicator assigned prior to the wirelessly transmitted packets being sent.

Abstract: Methods and systems for a programmable filtering offset may include filtering desired data located at a variable offset from a start of a particular message in a data stream using a programmable hardware filter module. The variable offset may be specified in bits or bytes. The programmable hardware filter module may start filtering from an offset corresponding to the start of the desired data. The programmable hardware filter module may be a variable length filter or a fixed length filter. An offset from the start of a particular message may be determined, where the desired data that may be compared may start after the offset from the beginning of the message. The programmable hardware filter module may be configured with the determined offset.

Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller.