Abstract: Permuted accelerated LDPC (Low Density Parity Check) decoder. This decoding approach operates by processing, in parallel, selected rows for multiple individual LDPC matrix rows from various sub-matrix rows (e.g., first group of rows from a first sub-matrix row, second group of rows from a second sub-matrix row, etc.). A memory structure of daisy chains is employed for memory management of APP (a posteriori probability) values and also for check edge messages/intrinsic information (?) values. A first group of daisy chains may be employed for memory management of the APP values, and a second group of daisy chains may be employed for memory management of the check edge messages. These daisy chains operate to effectuate the proper alignment of APP (or gamma(?)) values and check edge message/intrinsic information (?) values for their respective updating in successive decoding iterations.

Abstract: Systems and methods for performing a method for reducing power consumption in MoCA devices that are connected via a coax network are provided. One method according to the invention includes, in a home network having a plurality of network modules, one of said plurality of network modules being a network controller, each of said plurality of network modules being connected to a coax backbone, communicating over the coax backbone between the plurality of network modules. The method further includes using the master module to receive requests sent over the coax backbone from the plurality of network modules for bandwidth to transmit bursts. The master module may establish an order of transmission opportunities for the plurality of network modules to follow when transmitting bursts directly to other network modules via the coax backbone. The method may also include using the master module to toggle each of the networked modules between a running power state and a standby power state.

Abstract: A differential crystal oscillator circuit uses a bias transistor to generate a bias voltage from a bias current. The bias voltage is supplied to the control terminals of a differential pair of transistors. The differential transistors operate to produce a differential output between corresponding end terminals thereof, which is provided to a reference crystal oscillator to establish an oscillation frequency at the differential output.

Abstract: An apparatus may include a flow cache module that is arranged and configured to derive, at runtime, a custom sequence of code segments for packets belonging to a specific connection using a first packet of the specific connection and a parser module that is arranged and configured to identify packets as belonging to the specific connection using an Internet Protocol (IP) tuple of the packets, where the flow cache module is arranged and configured to apply the custom sequence of code segments to the identified packets.

Abstract: Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (?) values and check edge message (?) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.

Abstract: According to an example embodiment, an apparatus may include a client device including a processor and memory. The client device may be configured to obtain, via a secure communication, a certificate identifying a publically accessible wireless access point (AP) and a public key for the AP, the AP being publically accessible. The client (or client device) may be configured to generate a challenge, send the challenge to the AP, wherein the AP has a private key securely stored in a hardware security module of the AP. The private key may correspond to the public key for the AP. The client may be configured to receive a response from the AP, the response being generated by the AP based on the challenge and the private key for the AP, and authenticate the AP based on the response.

Abstract: Tail-biting turbo coding to accommodate any information and/or interleaver block size. A means is presented by which the beginning and ending state of a turbo encoder can be made the same using a very small number of dummy bits. In some instances, any dummy bits that are added to an information block before undergoing interleaving are removed after interleaving and before transmission of a turbo coded signal via a communication channel thereby increasing throughput (e.g., those dummy bits are not actually transmitted via the communication channel). In other instances, dummy bits are added to both the information block that is encoded using a first constituent encoder as well as to an interleaved information block that is encoded using a second constituent encoder.

Abstract: A system and method for changing retransmission and rescheduling queues to support retransmission in a communications system is presented. A method for changing queue size values includes, for an increase in data rate, determining a new retransmission queue size value for a retransmission queue at the transmitting device and a new rescheduling queue size value for a rescheduling queue at the receiving device such that an amount of time for a DTU to enter and exit the retransmission queue is greater than a roundtrip delay. For a decrease in data rate, the method includes determining the new retransmission queue size value and the new rescheduling queue size value such that an amount of time for a DTU to enter and exit the retransmission queue is less than a maximum delay. Systems and methods for changing the retransmission and rescheduling queue sizes are also presented.

Abstract: A wireless phone has a communication application that enables the phone to retain a phone number used in a first network when the phone switches association from the first network to a second network. Switching of network association by the phone is triggered by a user input entered via a user input interface of the phone. The phone directs the first network to not release the phone number upon disassociation of the phone from the first network, sends the phone number to the second network, directs the second network to identify the phone in second network by the phone number, and triggers the second network to attach a tag corresponding to the second network to the phone number and enter the tagged phone number in a central database. In another embodiment a subscriber identity module (SIM) enables the phone to use the communication application for phone number porting.

Abstract: A programmable network component for use in a plurality of network devices with a shared architecture, where the programmable network component includes an interface with an external processing unit to provide management interface control between the external processing unit and a network device. The programmable network component also includes a plurality of internal busses each of which is coupled to the programmable network component and to at least one network component. The programmable network component further includes a plurality of external buses each of which is coupled to the programmable network component and to at least one physical interface. The programmable network component is configured to support a plurality of protocols for communication with a plurality of physical interface components and comprises a plurality of programmable registers for determining the status of the plurality of physical interfaces.

Abstract: True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.

Abstract: An RF transceiver front-end includes receiver and transmitter front-ends. The receiver front-end includes 1st and 2nd antennas, a ninety degree phase shift module and an LNA module. The 1st and 2nd antennas receive inbound RF signals and provide a first directional circular polarization. The ninety degree phase shift module phase shifts the RF signals received by the 2nd antenna. The LNA module amplifies the RF signals received by the 1st antenna and the shifted RF signals. The transmitter front-end includes a PA module and 3rd and 4th antennas, which provide a second directional circular polarization. The PA module amplifies outbound RF signals to produce amplified outbound RF signals and amplified orthogonal outbound RF signals. The 3rd antenna transmits the amplified outbound RF signals and the 4th antenna transmits the amplified orthogonal outbound RF signals.

Abstract: A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a plurality of differential amplifiers configured to receive a plurality of input differential signals having different phases, and configured to generate a plurality of weighted signals responsive to the plurality of input differential signals. A plurality of digital-to-analog converters (DAC) are arranged into a plurality of groups, each group of DACs configured to provide current for one of the corresponding differential amplifiers. The number of active DACs in each group of DACs determines a relative weighting of the weighted signals, where relative weighting determining an output phase of an output signal of the phase rotator. The DACs are configured to adjust the output phase of the phase rotator. At a kth phase, N/4 adjacent DACs are activated that are indexed as m0, m1, . . . m((N/4)?1), wherein N is the number of said plurality of DACs.

Abstract: Presented herein is a method and system for reducing memory requirements in audio signal processing by de-interleaving audio information with at least two static buffers and a dynamic buffer. The method may include writing interleaved audio information to a first static memory device. The method may also include de-interleaving the audio information and writing de-interleaved audio information to a second static memory device. The method may also include writing de-interleaved audio information to a dynamic memory device from the second static memory device and overwriting interleaved audio information with new interleaved audio information in the first static memory device. The method may also include overwriting interleaved audio information in the first static memory device with de-interleaved audio information from the dynamic memory device and decoding the audio information.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A transmitter generates a transmitter output signal from first and second baseband signals. The transmitter includes a detector to detect a local oscillator (LO) leakage signal in the transmitter output signal. A controller coupled to the detector determines a direct LO coupling component and a baseband DC offset component of the LO leakage signal. First and second variable current sources are adjusted by the controller to provide first and second DC offsets to the first and second baseband signals, respectively. The first and second DC offsets reduce the direct LO coupling component. Third and fourth variable current sources are subsequently adjusted by the controller to provide third and fourth DC offsets to the first and second baseband signals, respectively. The third and fourth DC offsets reduce the baseband DC component. Overall, reducing the direct LO coupling component and the baseband DC component reduces a power of the LO leakage signal.

Abstract: The present invention relates to a system and method for implementing auto-configurable default polarity. More specifically, the present invention relates to a transceiver module comprising, for example, a single chip multi-sublayer PHY, where the single chip multi-sublayer PHY is adapted to implement auto-configurable default polarity. In one embodiment, the transceiver module comprises at least one program module adapted to be programmed with at least a default polarity setting. The single-chip multi-sublayer PHY comprises at least one selection register communicating with at least the program module, where the selection register is adapted to store at least the default polarity setting. The single chip multi-sublayer PHY further comprises at least one multiplexer communicating with at least the selection register and adapted to select one polarity from at least two possible polarities based at least in part on the default polarity setting.

Abstract: A system for reducing clock speed and power consumption in a network chip is provided. The system can have a core that transmits and receives signals at a first clock speed. A receive buffer can be in communication with the core and be configured to transmit the signals to the core at the first clock speed. A transmit buffer can be in communication with the core and configured to receive signals from the core at the first clock speed. A sync can be configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync can be in communication with the transmit buffer and the receive buffer.

Abstract: A sound quality metric may be determined at a near-end telephone system, the sound quality metric associated with far-end sound quality received at a far-end telephone system. A signal adjustment may be determined, based on the sound quality metric. The signal adjustment may thus be provided at an earpiece of the near-end telephone system. In this way, a user of the near-end telephone system may be alerted that the sound quality of a far-end user is unacceptably low, so that the near-end user may take corrective action at the near end to improve the far-end sound quality.

Abstract: Quasi-cyclic LDPC (Low Density Parity Check) code construction is presented that ensures no four cycles therein (e.g., in the bipartite graphs corresponding to the LDPC codes). Each LDPC code has a corresponding LDPC matrix that is composed of square sub-matrices, and based on the size of the sub-matrices of a particular LDPC matrix, then sub-matrix-based cyclic shifting is performed as not only a function of sub-matrix size, but also the row and column indices, to generate CSI (Cyclic Shifted Identity) sub-matrices. When the sub-matrix size is prime (e.g., each sub-matrix being size q×q, where q is a prime number), then it is guaranteed that no four cycles will exist in the resulting bipartite graph corresponding to the LDPC code of that LDPC matrix. When q is a non-prime number, an avoidance set can be used and/or one or more sub-matrices can be made to be an all zero-valued sub-matrix.