Abstract: A resonant power transmission system for wirelessly delivering electric power to a target device. A transmitter resonant phased array includes a power source operable to source alternating current power at a target frequency. A plurality of transmitting elements, each operable to produce a non-radiated magnetic field, produces a composite non-radiated magnetic field. A plurality of transmitter tuned circuit elements couple the alternating current power to the plurality of transmitting elements. Control circuitry controls the plurality of transmitter tuned circuit elements to direct the composite non-radiated magnetic field toward the target device. Communication circuitry communicates with the target device. The plurality of transmitting elements may be a plurality of coils with the control circuitry individually controlling phase of the non-radiated magnetic fields produced by the plurality of transmitting elements by control of the plurality of transmitter tuned circuit elements.

Abstract: A radio frequency (RF) transceiver front-end includes an antenna, an RF receiver section, an RF transmitter section, a balancing circuit, and a multiple node isolation and coupling circuit. The multiple node isolation and coupling circuit is coupled to the antenna, the RF receiver section, the RF transmitter section, and the balancing circuit. The multiple node isolation and coupling circuit provides an inbound RF signal from the antenna to the RF receiver section and provides an outbound RF signal from the RF transmitter section to the antenna, wherein, by providing an isolating signal to the balancing circuit, the multiple node isolation and coupling circuit substantially isolates the outbound RF signal from the inbound RF signal.

Abstract: In the current invention, an apparatus, method, and computer program product for allocating a contiguous area of memory from a repository are provided. In accordance with an embodiment of the invention, a repository pointer to a contiguous set of data blocks in the repository and a system pointer operable to point to the contiguous set of data blocks are allocated. The value of the repository pointer is subsequently assigned to the system pointer.

Abstract: In an integrated satellite receiver, improved header acquisition techniques are described for quickly locating a header symbol sequence in a data stream substantially implemented on a single CMOS integrated circuit. To identify the location of a header symbol sequence in a data stream, a selected header acquisition technique employs a real time correlator followed by an accumulator. Once accumulation over a predetermined number of frames is finished, the largest or maximum value among the accumulated correlator values is identified. If the maximum value exceeds a threshold, it will be declared as a peak and the address associated is the peak timing.

Abstract: A point-to-multipoint network interface is provided that is simpler and less costly to implement than conventional Ethernet switches. The interface includes a plurality of downstream transmitters for transmitting data packets to a plurality of end user devices, a plurality of downstream receivers for receiving data packets from the plurality of end user devices, an upstream transmitter and an upstream receiver. A multiplexer within the interface multiplexes data packets received from the end user devices into a stream of data packets for transmission to a higher level node regardless of the destination address of the data packets. Conversely, a demultiplexer within the interface demultiplexes a stream of data packets received from the higher level node into individual data packets for selective transmission to one of the plurality of end user devices. The interface can support asymmetrical transmission rates on the upstream and downstream channels between the interface and the end user devices.

Abstract: A system and method for detecting PES headers is presented herein. PES headers are detected by a combination of hardware and firmware. Hardware logic is used to detect the PES start codes while multithreaded firmware us used to process the packet.

Abstract: The present invention is directed to an improved memory and I/O bridge that provides an improved interface for communicating data between the data bus of the system processor and the memory controller. The memory and I/O bus bridge according to the present invention provides increased performance in the system. The memory and I/O bridge can include a deep memory access request FIFO to queue up memory access requests when the memory controller is busy. The memory and I/O bridge can include a memory write data buffer for holding and merging memory write operations to the same page of memory. The memory and I/O bridge can include a memory read data buffer for holding and queuing data and instructions read from memory, waiting to be forward to the data bus. The memory data read buffer can operate in one or more software selectable prefetch modes, which can cause one or more pages to be read in response to a single memory read instruction.

Abstract: A network device includes at least one first network port, at least one second network port, a MUX unit and a switching unit. The MUX unit is connected to the at least one first network port. The MUX unit includes a trunk circuit and an output. The trunk circuit is configured to aggregate data packets received at the at least one first port into a trunk group and to output trunked data packets to the output. The switching unit is connected to the output of the MUX unit and to the at least one second network port. The switching unit is configured to switch the trunked data packets to the at least one second network port.

Abstract: Clocking Chien searching at different frequency than other Reed-Solomon (RS) ECC decoding functions. An efficient implementation allows for a fast clock signal to govern the operation of the more computationally and time-intensive portions of the error correction code (ECC) time budget. For example, at least one module and/or decoding function within the ECC decoding is governed by using a first clock signal, and at least one other module and/or decoding function (or all the other modules and/or decoding functions) is/are governed by using a second clock signal. In one implementation of Reed-Solomon (RS) decoding, the Chien searching function is operated using a faster clock signal than at least one other RS error correction decoding function thereby allowing for a significant reduction in area and power than other architectural trade-offs.

Abstract: Aspects of a method and system for polar modulating OFDM signals with discontinuous phase may include amplifying an OFDM signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain and an amplitude offset gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain, and a gain of one or more remaining ones of the plurality of amplifiers may be adjusted to set the amplitude offset gain. The setting of the coarse amplitude gain and/or the amplitude offset gain may be adjusted dynamically and/or adaptively.

Abstract: A method of communicating data to a receiving antenna from N transmitting antennas, where N is an integer, includes the steps of determining whether a legacy transmission mode has been selected, producing N data streams from outbound data, and applying the N data streams to a space/time encoder to produce N encoded signals. When the legacy transmission mode has not been selected, the N encoded signals are transmitting from N transmitting antennas and when the legacy transmission mode has been selected, the one encoded signal is transmitted from one of the N transmitting antennas. The legacy transmission mode allows receivers to receive and process transmitted signals when the receivers are only configured to receive the transmitted signals from a single transmitting antenna.

Abstract: A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

Abstract: An FFT butterfly instruction based on single instruction multiple data (“SIMD”) technique is executed to reduce the number of cycles for software to perform FFT butterfly operations. The FFT butterfly instruction can implement one or more instances of the FFT butterfly operation (e.g., non-SIMD, 2-way SIMD, 4-way SIMD, etc.), at once, each instance operating over a set of complex values. A control register or variant opcode controls the behavior of the FFT butterfly operation. The contents of the control register or the variant opcode can be altered to configure the butterfly behavior to suit specific circumstances. The FFT butterfly instruction can be used in the software on a processor in a chip-set implementing the central-office modem end of a DSL link. The FFT butterfly instruction can also be used in other contexts where an FFT function is performed (and/or where an FFT butterfly operation is used) including systems that do not implement DSL or DMT.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: Managing packet data network jitter is disclosed. A first call data associated with a mobile network communication session is received. A second call data that is older than the first call data is dropped from a buffer if required to make room in the buffer for the first call data.

Abstract: Partial-parallel implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a selected number of cycles is performed during each of bit node processing and check node processing when performing error correction decoding of an LDPC coded signal. The number of cycles of each of bit node processing and check node processing need not be the same. At least one functional block, component, portion of hardware, or calculation can be used during both of the bit node processing and check node processing thereby conserving space with an efficient use of processing resources. At a minimum, a semi-parallel approach can be performed where 2 cycles are performed during each of bit node processing and check node processing. Alternatively, more than 2 cycles can be performed for each of bit node processing and check node processing.

Abstract: Discrete multitone transmission assigns bits to tones for transmission. The bits are assigned using permutations of bits and tones that cycle through a sequence of permutations in successive frames.

Abstract: A programmable attenuator includes a resistor ladder having a plurality of taps to provide a coarse gain control. Coupled to each tap is a plurality of switches. Control logic activates or deactivates individual switches in the plurality of switches to provide a fine gain control. More specifically, a set of activated switches provides fine gain control by determining an overall attenuation level interpolated between an adjacent pair of taps.

Abstract: A circuit and method to reduce jitter and/or noise in a phase-locked loop (PLL). A voltage-controlled oscillator (VCO) control signal is tapped and filtered to create a low-noise, filtered VCO control signal. The filtered and unfiltered control signals are individually weighted and then combined to create a modified VCO control signal which reduces the jitter and/or the noise by reducing an effect of VCO gain on the jitter and/or the noise.

Abstract: An integrated circuit package is provided. The integrated circuit package includes a heat sink, a cured silicone thermally conductive adhesive material, and a surface. The adhesive material attaches the heat sink to the surface. The surface is a surface of at least one of a substrate, a surface of an integrated circuit die, or a surface of an encapsulating material of the integrated circuit package.