Abstract: Aspects of a method and system for detecting Bluetooth signals utilizing a wideband receiver are provided. In this regard, a frequency band may be scanned by receiving signals on each of a plurality of sub-bands for an amount of time, the energy received in each band may be compared to a threshold, and whether each sub-band comprises a Bluetooth transmission may be determined based on a FFT. Additionally, the FFT may enable determining on which Bluetooth channel a detected transmission occurred. A FFT may be performed when energy detected in a sub-band is higher than a threshold. The sub-bands may each be a WLAN channel. A type of a detected Bluetooth transmission may be determined based on a number of scans in which the transmission is detected. Each sub-band may be received for less than or equal to 68 ?s divided by the number of sub-bands.

Abstract: A method and system for analog video noise reduction by blending finite impulse response (FIR) and infinite impulse response (IIR) filtering are provided. A filtering mode may be selected to generate noise-reduced pixels using FIR, IIR, or a blend of FIR/IIR filtering. Blending a current pixel and an FlR-filtered current pixel may generate a first blended current pixel. The FIR filtering may be based on the current pixel, a previous collocated pixel, and a next collocated pixel. Blending the current pixel and an IIR-filtered current pixel may generate a second blended current pixel. Blending the first blended current pixel and the second blended current pixel using an adaptive blending factor may dynamically generate a filtered output pixel. The IIR filtering may be based on the current pixel and a collocated pixel of the previous second blended video image or of the previous filtered output video image.

Abstract: A polar transmitter includes a digital processor for producing a phase correction signal and a complex modulated digital signal including a digital phase-modulated signal. The phase correction signal is added to the digital phase-modulated signal to produce a corrected digital phase signal. The corrected digital phase signal is input to a phase-locked loop (PLL) to produce an RF phase signal that tracks the phase of the digital phase-modulated signal based on the corrected digital phase signal.

Abstract: A multi-function appliance for use in a satellite navigation data distribution system is described. A computer includes an input/output interface and a memory the computer is configured with a plurality of modules. The plurality of modules includes a satellite signal receiver, a packetizer, a network interface, a concentrator, and a decoder. The satellite signal receiver is configured to obtain satellite navigation data from satellite signals. The packetizer is configured to packetize satellite navigation data to produce a reference packet stream. The network interface is configured to transmit packet streams towards a network. The concentrator is configured to remove duplicate packets within reference packet streams to generate a combined packet stream. The decoder is configured to decode satellite data from packet streams. In this manner, the computer may be configured to perform a reference station function, a hub function, or a server function in the satellite navigation data distribution network.

Abstract: A programmable antenna includes a fixed antenna element and a programmable antenna element that is tunable to one of a plurality of resonant frequencies in response to at least one antenna control signal. A programmable impedance matching network is tunable in response to at least one matching network control signal, to provide a substantially constant load impedance. A control module generates the antenna control signals and the matching network control signals, in response to a frequency selection signal.

Abstract: The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

Abstract: A channel selection canvas for display on a video display device is disclosed. The video display device can be a television, a laptop computer, or personal digital assistant device. The channel selection canvas allows a user to preview and choose video signals to be watched. The channel selection canvas displays a set of television channel video thumbnails, which can be full motion video, slow motion video or sampled video snapshots. A channel selection canvas can also display video thumbnails for security cameras, baby monitors, video phones and the like. A channel selection canvas generator that generates channel selection canvases is also disclosed. The channel selection canvas generator can reside within a television, set top box or similar video processing device.

Abstract: A method and system for simulation of an electronic circuit is provided, the circuit being represented by a network of a plurality of logic elements, the circuit comprising first and second asynchronous clock domains, whereby jitter elements are additionally inserted at predetermined portions of circuit boundaries between the first and second clock domains, the jitter elements being represented as logic elements, the values of which are randomly set.

Abstract: An apparatus, method, and system for DC offset cancellation are provided herein. For instance, the apparatus can include a first commutating mixer switch and a second commutating mixer switch. The first commutating mixer switch can have a first input port configured to receive a first differential signal and a first differential output port. The second commutating mixer switch can have a second input port configured to receive a second differential offset signal and a second differential output port. The first and second differential output ports can be coupled to one another to provide a combined differential output signal.

Abstract: The present invention provides a modular wireless headset with which to service multiple incoming audio streams. This modular wireless headset includes a wireless microphone and wireless earpiece. The wireless earpiece may exchange radio frequency (RF) signals with a base unit and render content contained within the exchanged RF signals to a user. This wireless earpiece further includes a wireless interface, a processor, a speaker, a user interface, and an authentication module. The wireless interface allows the earpiece to wirelessly communicate with the base unit. The processor recovers communications exchanged with the base unit that the speaker then renders audible. A user interface coupled to the processor may alert the user to any additional incoming audio communications. Having received the alert, the user may select between the communications.

Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a plurality of search engine pipeline stages, each of the plurality of search engine pipeline stages being configured to submit a particular search request to a plurality of search engines.

Abstract: There is provided a method of transferring a protected content, in which the method comprises receiving from a first player the protected content via a transmission medium calculating usage rights associated with the protected content to confirm receipt from the first player of some or all of the usage rights associated with the protected content making available the protected content for distribution to a second player, and transmitting the protected content to the second player. The method also includes confirming that the first player has relinquished the some or all of the usage rights associated with the protected content prior to transmitting the protected content to the second player. The protected content may comprise a music file, and the some or all of the usage rights may comprise a usage right for a limited number of protected content players, or comprise a usage right for a limited time duration.

Abstract: A method and apparatus are provided for enabling a transmitter to have a substantially linear magnitude response and a substantially linear phase response. The transmitter includes first and second power amplifier drivers (PADs) having respective first and second non-linear phase responses. The first non-linear phase response is based on a first bias applied to the first PAD, and the second non-linear phase response is based on a second bias applied to the second PAD. The first and second PADs are coupled in parallel to provide a combined substantially linear phase response. According to an embodiment, the first and second PADs have respective first and second average input capacitances. Signal swings about the first and second biases vary the respective first and second average input capacitances, which may be combined to provide a combined average input capacitance that is substantially insensitive to the signal swings about the first and second biases.

Abstract: Methods and associated systems provide secured data transmission over a data network. A security device provides security processing in the data path of a packet network. The device may include at least one network interface to send packets to and receive packets from a data network and at least one cryptographic engine for performing encryption, decryption and/or authentication operations. The device may be configured as an in-line security processor that processes packets that pass through the device as the packets are routed to/from the data network.

Abstract: Systems and methods for providing asymmetrical cryptographic acceleration are provided. The scalable asymmetric cryptographic accelerator engine uses a layered approach based on the collaboration of firmware and hardware to perform a specific cryptographic operation. Upon receipt of a request for a cryptographic function, the system accesses a sequence of operations required to perform the requested function. A micro code sequence is prepared for each hardware operation and sent to the hardware module. The micro code sequence includes a set of load instructions, a set of data processing instructions, and a set of unload instructions. An instruction may include a register operand having a register type and a register index. Upon receipt of a load instruction, the hardware module updates size information in a content addressable memory for a register included in the instruction. The hardware module continuously monitors the content addressable memory to avoid buffer overflow or underflow conditions.

Abstract: A system and method that optimizes a de-blocking filter process using local buffers. The local buffers may be off of the memory unit in which image data may be stored. The data associated with the image may be loaded into the local buffers. The data may be then fed into a filter, where the de-blocking filter process is executed, and the filtered data may be loaded back into the local buffers. The filtered data may then be written back to its original location in the memory.

Abstract: Provided is a system and method for performing smart offloads between computer applications module and a network interfacing device within a data communications system. The method includes receiving data requests from the computer applications module and determining whether the received data requests require offloading. The received requests are forwarded along a first data path to the network interfacing device if offloading is required. If offloading is not required, the received data requests are forwarded along a secondary data path to a host protocol stack for processing. Next, the protocol processing is performed and the processed data requests are forwarded to the network interfacing device.

Abstract: Methods, systems and computer program products for global address space management are described herein. A System-On-a-Chip (SOC) unit configured for a global address space is provided. The SOC includes an on-chip memory, a first controller and a second controller. The first controller is enabled to decode addresses that map to memory locations in the on-chip memory and the second controller is enabled to decode addresses that map to memory locations in an off-chip memory.

Abstract: Aspects of the invention may include gradually decrementing or incrementing a write pointer (370) associated with a data buffer such as the FIFO buffer (310) until a reset value of the write pointer (370) is reached in response to an indication that a data buffer controlled by the gray code counter is empty. Additionally, a read pointer (380) associated with the data buffer (310) may be gradually incremented or decremented until a reset value of the read pointer (380) is reached in response to an indication that the data buffer controlled by the gray code counter is full. The data buffer may be a first-in-first-out (FIFO) buffer such as FIFO buffer 310, which may be asynchronously clocked. The data buffer may be adapted to buffer any one or a combination of video, voice and data.

Abstract: Various embodiments are disclosed relating to wireless systems, and also relating to battery life improvement for wireless devices through activity report combining. According to an example embodiment, a method is provided. The method may include determining a reporting period, detecting user activity at each of a plurality of detection points within the reporting period, and transmitting a message for the reporting period over a wireless link to report the detected user activity for the plurality of detection points.