Abstract: Methods, systems and computer program products to maintain cache coherency in a System-On-a-Chip (SOC) which is part of a distributed shared memory system are described. A local SOC unit that includes a local controller and an on-chip memory is provided. In response to receiving a request from a remote controller of a remote SOC to access a memory location, the local controller determines whether the local SOC has exclusive ownership of the requested memory location, sends data from the memory location if the local SOC has exclusive ownership of the memory location and stores an entry in the on-chip memory that identifies the remote SOC as having requested data from the memory location. The entry specifies whether the request from the remote SOC is for exclusive ownership of the memory location. The entry also includes a field that identifies the remote SOC as the requester. The requested memory location may be external or internal to the local SOC unit.

Abstract: A method and apparatus are disclosed for performing motion estimation and compensation to fractional pixel accuracy using polyphase prediction filters as part of a video compression/decompression technique. A motion estimator applies a set of polyphase filters to some data in the reference picture and generates motion vectors, an estimated macroblock of video data, and a residual error macroblock of video data. The data referenced in the reference picture usually have more data than a macroblock since multi-tap filtering needs to access more data. A motion compensator generates a compensated macroblock of video data in response to the reference video data, the residual error macroblock of video data, and a polyphase prediction filter decided by the motion vector. The reference video data are usually reconstructed at the compensator side.

Abstract: Various embodiments are disclosed relating to wireless systems, and also relating to power control techniques for wireless devices. One disclosed embodiment comprises a wireless receiver that includes a processing circuit. In one example embodiment, at least a portion of the processing circuit may wake from a low power state to an operational state to receive and process only a portion of an ID packet during the operational state. The portion of the ID packet that is received and processed may be less than a full ID packet, which may provide power savings.

Abstract: A communications management system introduces a low bandwidth phase locked loop (LoBW-PLL) working in tandem with a high bandwidth phase locked loop (HiBW-PLL). The LoBW-PLL only needs to follow the average frequency of the transported clock and not all of the excursions made by the master clock. During periods of downstream outage, the LoBW-PLL opens its loop and free wheels such that disturbances caused by a reacquisition do not impact the concept of time for the LoBW-PLL. After reacquisition, the LoBW-PLL and HiBW-PLL are compared to determine if a timing error has occurred. If a timing error is detected, the magnitude of the timing error is measured upon completion of the reacquisition cycle, and this measurement is used to correct the timing error.

Abstract: A method and system to determine when a wireless terminal has been paged by a servicing base station. An encoded paging burst is received on a paging channel and then decoded to produce a decoded paging burst. The decoded paging burst is processed to determine if it is a null page. When the encoded paging burst is a null page, subsequent processing operations scheduled to follow a later null page are rescheduled and immediately processed, allowing the wireless terminal to re-enter the sleep mode more quickly following the receipt of a subsequent paging burst.

Abstract: LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.

Abstract: In a video system, a method and system for efficient design verification of a motion adaptive deinterlacer (MAD) are provided. A MAD reference model may be configured via a configuration file to generate test parameters for the verification of a MAD hardware model. Test-bench interface drivers and a verification monitor may be utilized to transfer test parameters to the MAD hardware model and to verify simulated results. Modes of verification may comprise a normal mode, a pixel processing mode, and a field controller mode. During the normal mode, simulated pixel information and register settings generated by the pixel processor and field controller in the MAD hardware model may be compared to expected pixel information and register settings generated by the MAD reference model. During the pixel processing mode, expected and simulated pixel information may be compared. During the field controller mode, expected and simulated register settings may be compared.

Abstract: A distributed CMTS includes a head end, a downstream transmitter hub, and an upstream receiver hub. The head end transmits data packets to the downstream transmitter via a coupling packet data network. Each data packet is marked with a “measured delay” Quality of Service (QOS) and includes a time stamp that is based upon a clock of the head end and a delay tag. The downstream transmitter hub receives the plurality of data, adjusts the time stamps based upon the delay tags, smoothes the time stamps of the plurality of data packets and, based upon the smoothed time stamps, synchronizes its clock with the clock of the head end. The downstream transmitter hub then synchronizes a clock of the upstream receiver hub with the clock of the downstream transmitter hub. The upstream receiver hub may synchronize its clock to the clock of the head end using this technique.

Abstract: Aspects of a method and system for parsing bits in an interleaver for adaptive modulations in a multiple input multiple output (MIMO) wireless local area network (WLAN) system are provided. The interleaver may generate a lookup table, which is utilized to assign at least one binary bit of information, among a plurality of binary bits of information to be transmitted, to at least one of a plurality of spatial streams. The lookup table may be utilized to assign binary bits of information among the plurality of spatial streams to improve performance of a MIMO transceiver.

Abstract: An automatic polarity swap is implemented in a communications system. Two or more transceivers having differential inputs and outputs are coupled together through an interface, such as a backplane to form a communications system. In such a configuration, it is possible to cross-connect the differential data lines or signals at the interface, which will cause invalid data words to received at the second transceiver. Accordingly, the present invention includes an error check and correction module that detects invalid data words after parallel-to-serial conversion. More specifically, an error check determines if the parallel differential signal represents a valid data word. This can be done, for example, by storing and comparing valid data words in a memory such as RAM. If the received data word is valid, then no corrective action is taken.

Abstract: A method and related computer program product of preventing write corruption in a redundant array in a computer system, comprising detecting a write failure from a calling application to at least one disk of the redundant array, writing failure information to non-volatile storage; returning an I/O error to the calling application; reading the failure information from the non-volatile storage during the next system reboot; and reconfiguring the array to eliminate the failed disk.

Abstract: An operational amplifier is provided with an extended common mode input range. This operational amplifier includes an input stage, a common mode feedback circuit, a current mirror, a replica input stage, and an output stage. The input stage couples to the CMFB circuit and replica input stage. The input stage is operable to receive a feedback signal from the CMBF circuit. This feedback signal is based on comparing a common mode voltage to a common mode reference voltage. The current mirror, coupled to the CMFB circuit and input stage, mirrors currents within the input stage as input to the CMFB circuit. The replica input stage, which is also coupled to the CMFB circuit, uses an input common mode (INCM) voltage to adjust current flow within the replica input stage. This allows a current within the CMFB circuit to be a function of the INCM. The output stage couples to the input stage and is operable to provide an amplified signal corresponding to a first differential signal.

Abstract: A method for decoding a word received at a current time instant into a symbol of a trellis code. The trellis code corresponds to a trellis diagram having N states associated with the current time instant. Each of the N states corresponds to at least one incoming branch. Each of the incoming branches is associated with a symbol of the trellis code. The branch metrics are computed for the incoming branches such that a branch metric represents a distance between the received word and a symbol associated with the corresponding branch. The branch metric is represented by fewer bits than a squared Euclidian metric representation of the distance. For each of the N states, a node metric is computed based on corresponding branch metrics and one of the incoming branches associated with the state is selected. One of the N states is selected as an optimal state based on the node metrics. The symbol associated with the selected incoming branch corresponding to the optimal state is the decoded word.

Abstract: A video processing device may comprise one or more processors and/or circuits for use in a video processing device, in which the one or more processors and/or circuits may comprise a video scaler, a memory, a scaler engine, a clock selection circuit. The one or more processors and/or circuits are operable to receive a video image and select a video input clock or a display output clock for upscaling the received video image, or select the video input clock or the display output clock for downscaling the received video image based on a determination of whether the video image is to be downscaled or upscaled. The one or more circuits may be operable to downscale the received video image to generate a first scaled video image, and/or upscale the received video image to generate a second scaled video image, based on the selection.

Abstract: A method and system to decode a video stream are provided. The method comprises receiving macroblocks, filtering and decimating the macroblocks to create decimated macroblocks and storing the decimated macroblocks. The method further comprises creating a decimated reference block from one or more decimated macroblocks of a decimated reference picture and interpolating selected pixels of the decimated reference block to create an interpolated reference block. The method further comprises pre-processing selected columns of the interpolated reference block to create a processed reference block for motion compensation.

Abstract: Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. A wafer has a surface defined by a plurality of integrated circuit regions Each integrated circuit region has a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer. An ink jet printer is configured to print a plurality of routing interconnects on the surface of a wafer in the form of an ink. The ink jet printer is configured to print the plurality of routing interconnects such that each routing interconnect has a first portion in contact with a respective terminal of the plurality of terminals and has a second portion that extends over the passivation layer. Bump interconnects are attached to the routing interconnects. The wafer may be singulated to create a plurality of wafer-level integrated circuits.

Abstract: Processing video data for delivery to a remote wireless includes receiving video data from a video source and receiving position and motion information regarding the remote wireless device. Operation also includes, based upon the position and motion information regarding the remote wireless device, determining an anticipated Quality of Service (QoS) available for servicing of transmissions to the remote wireless device and determining video processing parameters based upon the video data and the anticipated QoS. Operation further includes processing the video data based upon the video processing parameters to produce an output video stream and transmitting the output video stream for delivery to the remote wireless device. Operation may also/alternatively include altering wireless transmission parameters of a transport stream servicing delivery of the video data to alter the anticipated QoS.

Abstract: Various example embodiments are disclosed. According to an example embodiment, a method may include receiving data which has been encoded according to a first higher complexity protection scheme and compressed. The method may also include decompressing the data. The method may also include decoding the data according to the first higher complexity protection scheme using a first higher complexity key. The method may also include encoding at least the first portion of the data according to a second higher complexity protection scheme using a second higher complexity key. The method may also include encoding at least a second portion of the data according to a lower complexity protection scheme using a lower complexity key.

Abstract: A video processing device receives a request to forward a video stream from a video source to a remote wireless device and, based upon characteristics of the video stream, determines data throughput requirement sufficient to transport the video stream. The video processing device establishes a wireless communication link with the remote wireless device via a servicing wireless network with wireless link parameters that support the data throughput requirement. The video processing device may be required to establish/alter the wireless communication link with the remote wireless device via differing wireless link parameters that support a differing data throughput that is less than the data throughput requirement and process the video stream to alter its characteristics to meet the differing data throughput. In either case, the video processing device transmits the video stream to the remote wireless device via at least the differing wireless communication link.

Abstract: A system and method for inter-packet channel encoding/decoding for recovering lost packets, while minimizing network latency and delay. The novel inter-packet channel encoding/decoding scheme described herein operates on a running-basis. This running-basis scheme advantageously allows for a large number of packet losses to be corrected at a receiving node.