Abstract: The motherboard comprises a CPU and a memory component; further at least one video data processing chip mounted to the motherboard wherein the video data processing chip is programmable; and further at least one additional memory component provided to store a software that is executable by the video data processing chip.

Abstract: A system and method for dynamically reducing the precision of datapath modules within an FFT unit without adversely affecting the demodulation of an orthogonal frequency division multiplexing (OFDM) signal. An FFT unit is typically implemented in an OFDM receiver to separate sub-carriers within a received OFDM signal. In general, an FFT unit implemented within an OFDM receiver must be designed to operate with a precision high enough such that quantization noise, introduced within the FFT unit, does not dominate the overall maximum SNR requirement of the system. However, the SNR requirement for many OFDM receivers is dynamic and, as a result, OFDM receivers often have an instantaneous SNR requirement far below the required maximum. In these situations, it would be advantageous to reduce the precision of datapath modules within the FFT to conserve power, which is often limited in wireless devices.

Abstract: A disclosed embodiment is a CAM (content addressable memory) array with an invalidate feature, the CAM array includes a plurality of words, where each of the plurality of words includes a respective invalidate circuit. Each respective invalidate circuit is configured to invalidate stored data in each corresponding plurality of words if compare data on a data input bus uniquely identifies, i.e. matches, the stored data. Each of the plurality of words is coupled to the data input bus. In one embodiment, each invalidate circuit includes a memory cell which stores a valid bit to configure the invalidate circuit to invalidate the stored data in a respective word. Each of the plurality of words further includes a respective plurality of CAM cells, which store the stored data. Each CAM cell outputs a match signal that is coupled to a latch. The match signals are also coupled to corresponding invalidate circuits.

Abstract: A disclosed embodiment is a data retention flip flop comprising master and slave circuits that are configured to be turned off when a single sleep mode signal is activated. The disclosed embodiment also comprises an always-on balloon circuit coupled to the master circuit, where the always-on balloon circuit includes a common sub-circuit shared with the master circuit. The master circuit writes into the always-on balloon circuit when the single sleep mode signal is activated, and the master circuit reads from the always-on balloon circuit when the single sleep mode signal is deactivated. The always-on balloon circuits comprises high threshold voltage transistors, while the slave circuit comprises low threshold voltage transistors. The master and slave circuits have no leakage current, or substantially no leakage current, after the single sleep mode signal is activated.

Abstract: A system and method for regulating power consumption within an integrated circuit (IC) with a modular design. The IC is designed so that any one distinct functional module within the IC utilizes only transistors with a substantially same or similar critical voltage level, which may for example be the threshold voltage of the transistors. Consequently, the supply voltage delivered to each functional modules can be lowered to the minimum voltage necessary to enable the transistors within the module to operate. Similarly, modules within the IC may be designed with transistors which share a common value for a substrate bias voltage or a clock speed, or with a combination of common values for several electrical factors. In this way, it is possible to reduce power consumption by fine-tuning the voltages supplied to (or clock speeds driving) specific modules, in a way which is custom-tuned to each module.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB) or the communication ASIC to another communication ASIC. The high-speed bit stream interface includes a plurality of signal conditioning circuits. The signal conditioning circuits service each of an RX path and a TX path and include a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.

Abstract: A method and system for decoding WCDMA AMR speech data using redundancy may include generating at least one bit-sequence for at least one of a plurality of channels that comprises received WCDMA speech data. The bit-sequence may be generated by using a decoding algorithm and may be decrypted to recover the data that may have been encrypted before being transmitted. At least one bit-sequence may be selected for each of the channels by using redundancy, such as, for example, CRC, in the received WCDMA speech data. The redundancy in the received WCDMA speech data may be, for example, CRC. The bit-sequence for each of the channels may be combined to form at least one speech stream. A speech stream may be selected based on speech constraints, which may comprise gain continuity and/or pitch continuity. The selected speech stream may be communicated to a voice decoder.

Abstract: A transmitter includes a detection element to determine when a current power requirement of a communication link is less than the standard transmit power. The current power requirement may be determined by a current operation condition of the communication link, for instance. The transmit power of the transmitter may be set to be less than the standard power in any of a variety of ways. For example, a center tap voltage of the transmitter may be reduced. In another example, a class of operation of the transmitter may be changed. In yet another example, the transmitter may include a current mirror having a plurality of diode-connected transistors coupled in parallel, thereby reducing the current at output terminals of the transmitter. Reducing the current at the output terminals decreases the output power of the transmitter, which may reduce the power consumed by the transmitter.

Abstract: According to one embodiment, a system with a multi-purpose switch for providing a power on function and other functions to a user comprises a temporary power control circuit configured to be coupled to and decoupled from a power source by the multi-purpose switch. The system also comprises a continuous power control circuit to provide continuous power. As a result, the multi-purpose switch is capable of providing other functions when the continuous power is being provided. In one embodiment, a method for utilizing a multi-purpose switch to provide a power on function and other functions to a user comprises coupling a temporary power control circuit to a power source by the multi-purpose switch, triggering a continuous power control circuit to provide continuous power, decoupling the temporary power control circuit from the power source by the multi-purpose switch, and making the multi-purpose switch available to provide other functions.

Abstract: Methods and systems are provided that use smartcards, such as subscriber identity module (SIM) cards to provide secure functions for a mobile client. One embodiment of the invention provides a mobile communication network system that includes a mobile network, a mobile terminal, a server coupled to the mobile terminal via the mobile network, and a subscriber identity module (SIM) card coupled to the mobile terminal. The SIM card includes a first key and a second key. The first key is used to authenticate an intended user of the mobile terminal to the mobile network. Upon successful authentication of the intended user to the mobile network, the mobile terminal downloads a function offered from the server through the mobile network. The second key is then used by the mobile terminal to authenticate the intended user to the downloaded function so that the intended user can utilize the function.

Abstract: Various aspects of a method and system for transmission control protocol (TCP) traffic smoothing are presented. Traffic smoothing may comprise a method for controlling data transmission in a communications system that further comprises scheduling the timing of transmission of information from a TCP offload engine (TOE) based on a traffic profile. Traffic smoothing may comprise transmitting information from a TOE at a rate that is either greater than, approximately equal to, or less than, the rate at which the information was generated. Some conventional network interface cards (NIC) that utilize TOEs may not provide a mechanism that enables traffic shaping. By not providing a mechanism for traffic shaping, there may be a greater probability of lost packets in the network.

Abstract: A communication system performs burst noise cancellation. A transmitter produces and transmits a spread signal that comprises at least one known-value symbol spread by a plurality of non data-carrying orthogonal codes and data symbols spread by at least one data-carrying orthogonal code. The transmitter transmits the spread signal across a communication link that introduces burst noise. A burst noise detector determines burst noise affected chips of the orthogonal codes. A weight computation functional block calculates a plurality of complex-valued combining weights based upon the burst noise affected chips. A vector de-spreader and a linear combiner operate in combination to use the plurality of non data-carrying orthogonal codes, the at least one data-carrying orthogonal code, and the plurality of complex-valued combining weights to de-spread the received spread signal to produce the data symbols with the burst noise substantially removed.

Abstract: A novel means for performing dibit extraction is presented. Any one of an unequalized signal dibit, equalized signal dibit, or noise dibit can be extracted. Instead of using the correlation properties of a PN (Pseudo-Noise) sequence to approximate a PN deconvolution sequence, the use of the actual deconvolution sequence (i.e., PN sequence that includes values of +k and 0, where k is oftentimes 1) is employed so that no approximations are needed. The resulting estimate of the channel is therefore very accurate.

Abstract: A method and apparatus for communicating between devices is described. In one embodiment, the method comprises running two or more instances of a switch MAC sublayer on a switch and managing the two or more instances of the switch MAC sublayer as multiple logical access points inside the switch.

Abstract: A network switch for switching packets from a source to a destination includes a source port for receiving an incoming packet from a source, a destination port that contains a path to a destination for the packet, and a programmable counter unit for counting a number of packets of selected packet types which are received by the switch.

Abstract: Aspects of a method and system for processing audio and video transport may comprise synchronizing streams with associated program content based on 24-bit presentation time stamps (PTSs) and 32-bit system clock samples (SCSs) field without using decoding time stamps (DTSs). A PTS field may be provided as part of a packetized elementary stream (PES) packet syntax. An SCS field may be provided as part of a transport stream (TS) syntax. A system clock (STC) may be determined from received SCS values. Video and/or audio data may be decoded as soon as they arrive and when there is at least one display and/or presentation frame buffer available. The video and/or audio data may be presented for display and/or play based on a comparison of the PTS and STC values. When a frame does not have an associated PTS, a PTS extrapolation operation may generate an extrapolated PTS value from previously received PTSs.

Abstract: The present invention provides an equalizer processing module within a wireless terminal having an equalizer interface that receives an incoming baseband signal from a baseband processor operably coupled to the equalizer processing module and outputs soft decisions. A processor or advanced reduced instruction set computer (RISC) machine (ARM) couples to the equalizer interface while an equalizer accelerator module operably couples to the processor or ARM. Processing of the incoming baseband signal to produce soft decisions is performed by the combination of the processor and equalizer accelerator module. A sample capture buffer and an equalizer output buffer which may or may not be within the equalizer processing module allow data to be sampled and serves as the input and output for the equalizer processing module. This equalizer accelerator may specifically perform compute intensive operations such as Trellis computations for MAP equalization or MLSE equalization.

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) collection module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract: A voice data and RF integrated circuit (IC) includes a memory module that stores a least one application as a plurality of operational instructions, the at least one application having a plurality of power modes that each correspond to one of a plurality of use characteristics. A processing module executes the plurality of operational instructions, determines a selected one of the plurality of power modes based on current use characteristics of the at least one application, and generates a power mode signal based on the selected one of the plurality of power modes. An on-chip power management circuit receives the power mode signal and generates a plurality of power supply signals based on the power mode signal.

Abstract: Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.