Abstract: Certain embodiments of a method and system for handling connection setup in a network may comprise a host that generates connection acceptance criteria and/or a services list that may be transferred to a network interface hardware device for determining whether a remote peer connection request may be accepted. The network interface hardware device may generate connection primitives to complete the network connection setup after accepting the connection request. The network interface hardware device may wait for a response from the host before generating the connection primitives. The network interface hardware device may copy the host during connection setup. The host may provide and indication to the network interface hardware device to deny the connection request or to drop the connection after the connection has been setup. The network interface hardware device may maintain a connection state generated when the connection setup is completed.

Abstract: A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

Abstract: A method and computer program product for detecting faults in cables. The invention comprises receiving a first reflected signal; comparing the first reflected signal amplified with a first predetermined receiver gain setting with a first threshold; if the value of the amplified first reflected signal is greater than the value of the first threshold, then terminating detecting; if the value of the amplified first reflected signal is not greater than the value of the first threshold, then comparing a second reflected signal amplified with a second predetermined gain setting different from the first gain setting with a second threshold.

Abstract: Aspects of a double search user group selection scheme with range reduction for FDD multiuser MIMO downlink transmission with finite-rate channel state information feedback are provided. The method may comprise maximizing system capacity using feedback information for a plurality of signals in a frequency division duplex system to reduce a search range within which a group of signals having maximum channel gain are located. The feedback information may comprise quantized gain for the signals. Quantized channel direction for the signals within the reduced search range may be requested and received by the transmitter. One or two signals from the reduced search range that maximizes system capacity may be selected. The receivers associated with these signals may then be selected as the user group.

Abstract: A direct conversion tuner down-converts television signals, cable signals, or other signals directly from an RF frequency to an IF frequency and/or baseband, without an intermediate up-conversion step for image rejection. The direct conversion tuner includes a pre-select filter, an amplifier, an image reject mixer, and a poly-phase filter. The pre-select filter, amplifier, and the image reject mixer can be calibrated to provide sufficient image rejection to meet the NTSC requirements for TV signals. The entire direct conversion tuner can be fabricated on a single semiconductor substrate without requiring any off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: Methods and systems for reconfigurable soft-output bit demapping, reconfigurable for different modes of operation (i.e., different transmitter/receiver configurations) and for different modulation schemes are provided. In an embodiment, a reconfigurable soft-output bit demapping system includes a mode/modulation independent equalizer, a plurality of mode/modulation independent soft-slicers coupled to the outputs of the equalizer, a plurality of mode/modulation independent post-scalers coupled to the outputs of the soft-slicers, and a mode-dependent coefficient calculator. The coefficient calculator generates parameters for configuring the equalizer, the soft-slicers, and the post-scalers according to the used mode of operation and modulation scheme.

Abstract: Systems and methods are disclosed for filter modules in a video display system or network. One embodiment relates to a method for operating a filter module in a video display network comprising determining a picture type, display type and operation of the display network. The method further comprises determining, in real time, a filter configuration from a plurality of possible filter configurations based on the determined picture type, display type and operation.

Abstract: A network component for processing a packet can include a buffer configured to receive a packet, a forwarding unit configured to forward the packet received at the first buffer to a loopback port, and a transmitting unit configured to transmit the packet out of the loopback port. In addition, the network component can include a loopback unit configured to loop back the packet into the loopback port, a first identification unit configured to identify an egress port, and a second transmitting unit configured to transmit the packet looped back from the loopback port out of the egress port.

Abstract: The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data. The system and method includes acquiring the width in data elements of a digital data burst and the width in data elements of a data block of higher speed digital data. The width of one period of a clock pulse is computed at the first clock frequency. A clock pulse is generated at the first clock frequency.

Abstract: Digital signal processing based methods and systems for receiving electrical and/or optical data signals include electrical receivers, optical receivers, parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a single path receiver. Alternatively, the present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal.

Abstract: A frequency synthesizer for use in a transmitter operates to receive outbound transmit data and to modulate the outbound transmit data to produce a modulated RF signal. The modulated RF signal can then be amplified to produce an outbound RF signal.

Abstract: Methods and systems for blocker attenuation using multiple receive antennas are disclosed. Aspects of one method may include receiving wideband signals multi-antenna receiver. The receiver may process received signals that may comprise blocking signals received via the multiple antennas. The blocker received by a first antenna may be suppressed, at least in part, by combining processed signals received by a first antenna with processed signals received by a second antenna. The combining may comprise, for example, adding the two processed signals at either the RF or IF frequencies. The processing of the signals whose blocker is to be suppressed may be gain adjustment. The processing of the other signals used to suppress the blocker of the first antenna may be gain and/or phase adjustment. Accordingly, a blocker received by any antenna may be suppressed, at least in part, by using processed signals received by another antenna.

Abstract: A multi-stage amplifier assembly configured to receive a terrestrial digital television (“DTV”) input signal including multiple frequency channels. The amplifier assembly optionally includes a PIN diode coupled across differential inputs to a first stage of the multi-stage amplifier assembly. The PIN diode is controlled to attenuate the input when an exceptionally large signal is present in a channel adjacent to a desired channel. The PIN diode, essentially a variable resistor, permits the multi-stage amplifier assembly to maintain dynamic range in such situations for reasonable tradeoffs. The amplifier assembly further optionally includes an out-of-band second stage LNA. The amplifier assembly further optionally includes a multi-band input filter. The multi-band filer insures that the AGC operates on the TV band of interest, thus improving the linearity of the system. The invention can be implemented in CMOS and/or SiGe.

Abstract: A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern.

Abstract: Aspects of a method and system for a fractional-N synthesizer for a mobile digital cellular television environment are presented. Aspects of the system may include circuitry, within a phase locked loop, that enables determination of a division number at a time instant within a division cycle. A local oscillator signal may be modified based on the division number in a succeeding division cycle. A subsequent local oscillator signal may be generated based on the modification.

Abstract: A receiver front end includes a plurality of in-phase and quadrature phase receive processing blocks operable at first and second frequency bands and further includes a plurality of filtering and amplification blocks disposed within a corresponding ingoing signal path, a plurality of received signal strength indicator (RSSI) blocks coupled to receive an ingoing analog signal from a corresponding plurality of nodes disposed throughout the ingoing signal path, each of the plurality of RSSI blocks producing a signal strength indication, and wherein a baseband processor is operable to receive a selected signal strength indication and to produce at least one gain setting to at least one amplification block within the in-phase or quadrature phase receive processing blocks. In operation, the baseband processor receives a signal strength indication from each RSSI block to determine a total amount of gain and appropriate gain distribution within the receive signal path.

Abstract: Presented herein are ball grid array configurations for reducing path distances. In an exemplary embodiment, there is presented a memory system. The memory system comprises a printed circuit board, a memory controller, and a memory. The printed circuit board comprises a first layer and a second layer. The memory controller comprises a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer. The memory comprises a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer. The first layer comprises a plurality of connection paths connecting the first plurality of pins of the memory to the first plurality of pins of the memory controller. The second layer comprises a plurality of connection paths connecting the second plurality of pins of the memory to the second plurality of pins of the memory controller.

Abstract: A data communication network for providing dynamic routing through both wireless and wired subnetworks to support wireless communication devices and wired remote stations is disclosed. In the wireless network, the wireless communication devices can be mobile RF terminals, while the wired remote stations might be personal computers attached to a wired subnet, such as an ethernet coaxial cable. The wireless network architecture utilizes a spanning tree configuration which provides for transparent bridging between wired subnets and the wireless subnets. The spanning tree configuration provides dynamic routing to and from wireless communication devices and remote stations attached to standard IEEE 802 LANs.

Abstract: Certain aspects of a method and system for independent in-phase (I) and quadrature (Q) loop amplitude control for quadrature generators may include determining an amplitude voltage associated with an in-phase (I) component and a quadrature (Q) component of a generated signal. A DC reference voltage associated with the I component and the Q component may be determined. The determined amplitude voltage may be compared with the determined reference voltage to generate a control signal. The amplitude mismatch between the I component and the Q component may be compensated by controlling a biasing current of one or more programmable buffers associated with one or both of the I component and the Q component, based on the generated control signal.

Abstract: The present invention relates to a mobile set integrating a memory efficient data storage system for the real time recording of voice conversations, data transmission and the like. The data recorder has the capacity to selectively choose the most relevant time frames of a conversation for recording, while discarding time frames that only occupy additional space in memory without holding any conversational data. The invention executes a series of logic steps on each signal including a voice activity detector step, frame comparison step, and sequential recording step. A mobile set having a modified architecture for performing the methods of the present invention is also disclosed.