Abstract: A switchboard device and methods of operation of same are disclosed. Embodiments of the invention may provide a flexible means of interconnecting wideband and narrowband communications interfaces, where wideband communications interfaces may transfer wideband data sampled at a higher sampling rate, and narrowband communication interfaces may transfer narrowband data sampled at a lower sampling rate. Data streams sampled at different sampling rates can be combined and the sampling rate of the result adjusted as needed by the destination interface. Methods of operating embodiments of the present invention are included. An additional aspect of the present invention may include machine-readable storage having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the foregoing.

Abstract: The present invention provides systems and methods for asymmetrically varying gain in a low noise amplifier. The amplifier includes a first stage amplifier, a plurality of second stage amplifiers coupled to the first stage amplifier, a comparator coupled to one of the second stage amplifiers, and a controller coupled to the comparator, the first stage amplifier, and the plurality of second stage amplifiers. The controller is configured to produce one or more gain control signals to change the gain of one of the first stage amplifier or the plurality of second stage amplifiers at a plurality of asymmetric rates so as to cause the power of the output signal to move toward one of the threshold values of the comparator. The rate of change of the gain is based on conditions including the gain of the first stage amplifier, gain of a second stage amplifier, and the sampled power level.

Abstract: An RFIC transmitter includes a digital transmit processing module, a digital to analog converter, a filter and gain module, an up-conversion module, a power amplifier, and a transmit signal strength module. The transmit signal strength module is coupled to generate a gain adjust signal based on a measure of transmit power of an outbound RF signal, wherein the transmit signal strength module provides the gain adjust signal to at least one of the digital transmitter processing module, the digital to analog converter, the filter and gain module, the up-conversion module, and the power amplifier.

Abstract: Systems having a user interface comprising a filtered view of media available for consumption is disclosed. An embodiment of the present invention may provide a first user with a view that enables consumption of only the available media that matches characteristics of a media filter. The characteristics of the media filter may be specified by a second user, and the second user may define the characteristics of the media filter remotely, via a communication network. The user interface may support separate media filters for each of a number of different users. Filter characteristics such as type of media channel, the language of any dialogue, an industry rating, an overall viewer rating, and the media format may be supported. The media filter characteristics may be applied not only to what is displayed on the user interface, but also the media available for selection via a remote control.

Abstract: A method for calibrating a radio frequency (RF) transmitter begins by mixing a modulated RF signal with an in-phase (I) component of a local oscillation or a quadrature (Q) component of the local oscillation to produce a baseband representation of the modulated RF signal. The method continues by converting the baseband representation of the modulated RF signal into a digital baseband signal. The method continues by filtering the digital baseband signal to produce at least one frequency spectrum component. The method continues by interpreting the at least one frequency spectrum component to produce a calibration signal. The method continues by calibrating at least one of DC offset and gain offset of digital transmitter processing module based on the calibration signal.

Abstract: An integrated radio circuit includes a receiver section, a transmitter section, an analog to digital converter section, a digital to analog converter section, a digital baseband processing module, a first dual function input/output (I/O) module, and a second dual function I/O module. The first dual function input/output (I/O) module is operably coupled to provide inbound digital baseband signals as selected inbound digital baseband signals to the digital baseband processing module when the integrated radio circuit is in a normal mode of operation and to provide test inbound digital baseband signals as the selected inbound digital baseband signals to the digital baseband processing module when the integrated radio circuit is in a test mode.

Abstract: Aspects of the invention provide a method and system for a mixed analog-digital automatic gain control. The received analog signal is amplified by the analog amplifier and then converted to a digital value by an ADC. A clamp reference level of the converted signal is removed prior to applying a digital gain to a digital multiplied. Once the digital gain is applied, the clamp reference level is restored to the digital signal. A loop filter determines the system time response from the error between an amplitude parameter of the received signal and an AGC reference level. A gain separation circuit generates the system gain and separates it into a digital gain and an analog gain in a way to maximize the use of the analog amplifier. The analog gain is applied to the analog amplifier and the digital gain is applied to the digital multiplier.

Abstract: A method for designing an integrated circuit having analog and digital circuit portions is disclosed. The method involves providing an emulation circuit, which preferably comprises a number of gates equivalent to a number of gates in the digital circuit portion, affixing the emulation circuit on a test substrate together with a version of the analog circuit portion having at least some of the defined functions of the analog circuit portion, and then testing the analog circuit version.

Abstract: Efficient design to implement LDPC decoder. The efficient design presented herein provides for a solution that is much easier, smaller, and has less complexity than other possible solutions. The use of a ping-pong memory structure (or pseudo-dual port memory structure) in conjunction with a metric generator near the decoder's front end allows parallel bit/check node processing. An intelligently operating barrel shifter operates with a message passing memory that is operable to store updated edges messages with respect to check nodes as well as updated edges messages with respect to bit nodes. Using an efficient addressing scheme allows the same memory structure to store the two types of edges messages with respect to bit nodes: (1) corresponding to information bits and (2) corresponding to parity bits. In addition, an intelligently designed hardware macro block may be instantiated a number of times into the decoder design to support ever greater design efficiency.

Abstract: A super set of orthogonal space-time block codes is combined with set partitioning to form super-orthogonal space-time trellis codes having full diversity, enhanced coding gains, and improved rates. In communications systems, these codes are implemented by an encoder of a diverse transmitter to send an information signal to a receiver having one or more receiver elements. A decoder in the receiver decodes the encoded signal to reproduce the information signal. A method of the invention is used to generate set portioning structures and trellis structures that enable code designers to systematically design the codes of the invention.

Abstract: A system and method for controlling performance and/or power based on monitored performance characteristics. Various aspects of the present invention may comprise an integrated circuit comprising a first circuit module that receives electrical power. A second circuit module may monitor one or more performance characteristics of the first circuit module and/or the integrated circuit. A third circuit module may, for example, determine power control information based at least in part on the monitored performance characteristic(s). The power control information may be communicated to power supply circuitry to control various characteristics of the electrical power. Various aspects of the present invention may also comprise an integrated circuit comprising a first module that monitors at least one performance characteristic of a first electrical device.

Abstract: A media access controller, which includes an output buffer and a clock controller, is provided. The output buffer includes a first and second clock input. The first clock is configured to control data input into the buffer and the second clock is configured to control data output from the buffer. The clock controller is coupled to the output buffer and configured to regulate a first clock signal input into the first clock input to control the data input into the buffer.

Abstract: A polyphase filter including M taps, each of the M taps including a filter coefficient. The filter also includes a multiplier-accumulator (MAC) shared by the M taps, a plurality of multiplexors for sequentially selecting a subset of the plurality of taps, and a scheduler for controlling the MAC to perform arithmetic operations on respective filter coefficients of the selected subset of the plurality of taps.

Abstract: A system and method for providing upstream adaptive modulation. Burst parameters associated with a range of data interval usage codes (IUCs) are defined. Each of the data IUCs has a different modulation order and forward error correction (FEC). The SNR and codeword error rate for each satellite modem in the network are monitored. The data IUCs are dynamically assigned to different satellite modems within an upstream channel based on SNR and/or codeword error rate to enable each of the satellite modems in the upstream channel to achieve maximum bandwidth efficiency during upstream data transmissions. Bandwidth requests are received from the satellite modems and granted. The grant includes the assigned data IUC. The data bursts received in the upstream channel are each processed using the parameters from the assigned IUC for each of the satellite modems sending data in the upstream channel.

Abstract: A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer.

Abstract: A radio frequency (RF) bus controller includes an interface and a processing module. The interface is coupled for communicating intra-device RF bus access requests and allocations. The processing module is coupled to receive an access request to an RF bus via the interface; determine RF bus resource availability; and when sufficient RF bus resources are available to fulfill the access request, allocate, via the interface, at least one RF bus resource in response to the access request.

Abstract: An RF transceiver system includes a configurable antenna system that includes an antenna control module that is capable of controlling the configurable antenna system, in response to a control signal, to each of a plurality of antenna configurations. An RF receiver receives a received signal from the configurable antenna system in a receive mode and generates inbound data from the received signal, the inbound data including received antenna control data received from a first remote station. A processing module generates the control signal in response to the received antenna control data to command the antenna control module to control the configurable antenna system to a selected one of the plurality of antenna configurations.

Abstract: A device includes a plurality of ICs and an RF bus structure. Each IC includes a plurality of circuit modules, a switching module, an RF bus transceiver, an antenna interface, and an antenna structure. The switching module provides controlled access to the RF bus transceiver, which communicates via the RF bus structure, among the plurality of circuit modules for external IC communications and provides connectivity among the circuit modules for internal IC communications.

Abstract: An integrated circuit includes an on-chip antenna interface, coupled to an off-chip antenna interface having at least one off-chip filter component that forms a programmable filter with the at least one off-chip filter component. The programmable filter is programmable based on a control signal. An RF receiver generates inbound data in response to a received signal from the programmable filter.

Abstract: A (radio frequency) RF reception system includes an off-chip antenna interface and an integrated circuit. The an off-chip antenna interface includes at least one first off-chip impedance matching component, a filter, and at least one second off-chip impedance matching component. The integrated circuit includes an on-chip antenna interface that forms a first programmable impedance matching network with the at least one first off-chip impedance matching component, and forms a second programmable impedance matching network with the at least one second off-chip impedance matching component. The first programmable impedance matching network and the second programmable impedance matching network are programmable based on a frequency selection signal.