Abstract: According to an example embodiment, an amplitude feedback loop may include an RF amplifier, a detector, a comparator, and a Q-enhancement cell. In an example embodiment, the RF amplifier has an output signal, and the detector has an input coupled to the output signal of the RF amplifier and is configured to detect a level of the output signal of the RF amplifier. The comparator circuit may receive as inputs a reference voltage and the output of the detector. Also, the comparator circuit is configured to output a control signal based on a difference between the reference voltage and the output signal of the power detector. The Q-enhancement cell may be coupled to the RF amplifier and have an input coupled to an output of the comparator circuit. A bias current of the Q-enhancement cell may be adjusted based on the control signal output by the comparator circuit.

Abstract: Methods and apparatus are provided for implementing a cryptography accelerator for performing operations such as hash operations. The cryptography accelerator recognizes characteristics associated with input data and retrieves an instruction set for processing the input data. The instruction set is used to configure or control components such as MD5 and SHA-1 hash cores, XOR components, memory, etc. By providing a cryptography accelerator with access to multiple instruction sets, a variety of hash operations can be performed in a configurable cryptographic accelerator.

Abstract: A counter system and method and computer program product for managing counter systems. Counter systems management includes receiving a count event associated with a counter, updating a first stage counter value based on the count event, determining whether to eject the counter value based on a random function of the counter state, and ejecting the counter value. A counter system comprises a first stage update unit configured to accept a count event and to eject a counter. A second stage update unit may be configured to accept an ejected counter value, and includes a second counting module configured to accumulate the ejected counter value.

Abstract: Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation. A novel means is presented herein by which error magnitudes (or error values) can be calculated directly without requiring the generation of an error value polynomial (EVP). Modification of the Koetter decoding approach and the Forney formula are employed herein to perform the direct calculation of the error values. This approach is operable to save computation clock cycles that would normally be used to compute the EVP, and these clock cycles may be used to reduce the otherwise required parallelism and complexity in the ECC design that may be needed to perform the error correction in the allotted time and may also result in power savings. Some advantages related to this may approach include lower risk, less design time, and more scalability in an overall design.

Abstract: A system and method of classifying a high powered device (PD) with an increased current limit includes: connecting a voltage to the PD, measuring current through a classification resistor connected to the PD, and determining a PD classification signature based on the current according to classification steps such that a minimum classification step includes a minimum current of 0 mA and a maximum classification step includes a maximum current beyond a predetermined current limit. The system includes a PSE, voltage source, PD classification resistor, and PD voltage, connected to the P. An alternative embodiment further includes a discrete classification circuit and discrete classification resistor to be used to measure the current for classification purposes instead of the PD classification resistor when the PD and PD classification resistor do not support power classification under the classification scheme.

Abstract: Area efficient on-the-fly error correction code (ECC) decoder architecture. A novella means is presented by which only 2 banks of registers are employed (as opposed to 3 or more banks) when generating an error location polynomial in accordance with decoding of a Reed-Solomon (RS) coded signal. Berlekamp-Massey decoding processing can be employed when decoding such a RS coded signal. This approach provides for a significant amount of savings in hardware. For example, one embodiment designed in accordance with the invention is operable to implement an entire 12-bit (t=120) Reed-Solomon ECC system for HDD applications which consumes only approximately 170 k gates. Of these 170 k gates, 70K gates are attributed to the syndrome/symbol computer. Moreover, because of the pipelined arrangement of the decoding processing presented herein (which allows for more clock cycles to perform the division), division processing can be performed using an inverter and multiplier.

Abstract: An integrated circuit radio transceiver and method therefor includes capacitive loop filter with selectable capacitive elements that are operable to adjust a signal level provided to a voltage controlled oscillator to control a frequency of an output signal of the oscillator. A plurality of switches are controlled by logic to define a discharge mode, a charge mode and charge sharing mode in which a plurality of capacitive elements share charge while generating the input voltage to the oscillator.

Abstract: A technique to detect head instability by monitoring for a baseline popping (BLP) noise effect on demodulation bursts read from a disk. In one technique, a digital filter is employed as a moving average filter so that the filtering of the bursts has a zero output from the filter if only the bursts are present. However, when a BLP event occurs, the noise effect causes a non-zero output from the filter. A threshold value is set and when the output of the filter exceeds the threshold value, a BLP indication is noted. Although various filters may be used, in one technique, a filter suitable for use in detecting thermal asperity defects is used for the BLP detection filter.

Abstract: A technique to detect defects when reading a defect scan pattern stored on a disk in which the detected defects are processed differently depending on which region of a sector the defect is resident. In one implementation, a mask is used to identify the defects of different regions. By differentiating different regions within the sector for defect scan, sync mark and preamble fields may be treated as critical regions so that different defect scan properties may be attributed when performing the defect scan.

Abstract: A system and method for managing memory resources in a system that allows remote direct access of memory. An aspect of the invention provides for automatically un-binding bound direct-access memory resources based on information received in messages from a remote source. The information may, for example, include a last-segment indicator to indicate that the message segment is the last expected message segment for a message. Another aspect of the invention provides for memory management of directly-accessible sections of memory by assigning a flag to indicate when the section of memory has special access restrictions, such as a set number of allowable accesses. Yet another aspect of the invention provides for a flag to represent when the access restrictions associated with a particular section of memory have been met.

Abstract: An integrated circuit radio frequency (RF) transmitter includes a phase locked loop having a multi-mode loop filter that is operable to provide wide band response with a fast settle time in a startup mode of operation and a relatively more narrow response with a longer settle time but with improved filtering in a steady state mode of operation according to one embodiment of the invention. The multi-mode loop filter includes, in one embodiment, selectable resistance circuitry for selecting between a plurality of resistance values based upon a two-state multi-mode control signal to provide the selected resistance values and selectable capacitance circuitry for selecting between a plurality of capacitance values based upon the two-state multi-mode control signal and for operatively coupling selected capacitors to selected resistors to provide the selected capacitance values.

Abstract: An impairment compensation sequence for use in a communication system susceptible to one or more potential impairments each periodic in an integer number of symbols includes N phases, wherein N is selected such that each potential impairment, if present, is periodic therein, and a sequence of symbols, the sequence organized to place at least one instance of each symbol from a predetermined set of symbols in each phase to allow detection of the potential impairments in each of the N phases. The potential impairments may include robbed-bit signaling and padding. Using estimates prepared based on such an impairment compensation sequence, individual phase intervals may be grouped according to similarity of apparent aggregate effect of the impairments thereon without identification of individual impairments active in the particular phases. Constellation points may then be assigned based on group characteristics corresponding to phase intervals.

Abstract: A Finite Impulse Response (FIR) filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods. In particular, an efficient implementation for a general purpose processor having a substantial number of registers includes inner and outer loop code which together make K ? [ ( L 1 + L 2 L 1 ? L 2 ) ? N + L 2 L 1 + 1 ] memory accesses and KN multiply-accumulates, where L1 is the number of output vector elements computed during each pass through the outer loop and where L2 is the number of taps per output vector element computed during each pass through the inner loop. The efficient implementation exploits L1+2L2 general purpose registers.

Abstract: The present invention implements an architecture that changes the sequence of digital processing so that equalization occurs prior to phase accumulation. A phase differentiator receives an envelope path phase signal to produce a differentiated phase signal to an equalizer. The transfer function of the phase differentiator is implemented so that it cancels, except for a one-cycle delay, the transfer function of the phase accumulator. This cancellation substantially eliminates accumulation of the envelop path phase signal. Additionally, a dither signal added to the quantization nodes in the equalizers shifts the spectral content of the quantization noise such that the phase accumulator sees the quantization noise as zero mean white noise. Implemented as one of a rounding or flooring quantizer, biquad filters in the equalizers round or truncate the equalizer output to a minimal bit width based on a desired output phase error.

Abstract: In a video system, a method and system for cross-chrominance removal using motion detection are provided. A luma motion detector in a motion adaptive deinterlacer may be used to determine a chroma current motion for a pixel in a video frame. The chroma current motion may be modified, based on a chroma motion mechanism comprising of an edge detection, a back-off, and a motion biasing, when the output pixel is found to be in a static chroma area of the video frame. A static chroma threshold parameter may be used to determine whether the output pixel is in a static chroma area. A cross-chroma reduction determined based on the current chroma motion, may be blended in the motion adaptive deinterlacer with a spatial average approximation of the output pixel to remove the cross-chrominance from the output chroma.

Abstract: Certain aspects of the invention provide handling out-of-order TCP segments and may include placing a first received segment in a host buffer and determining whether a second received segment is an in-order or out-of-order (OOO) segment. Control information associated with OOO segments may be stored locally on a network interface card (NIC) and the OOO segment placed in a host buffer rather than on the NIC. An address or location occupied by an end of the first received segment may be recorded and stored on the NIC. As in-order and/or OOO segments are received, control information associated with a starting address and/or end address may be stored on the NIC. Accordingly, as subsequent in-order and/or OOO segments are received, they may be correctly placed within the host buffer based on the recorded and/or stored control information without being buffered on the NIC.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: Certain aspects of determining a signal quality metric in event of a CRC false positive may comprise measuring an amplitude and/or phase of at least a portion of a phase shift keyed section of a frame. The measured amplitude and/or phase may be checked to determine if it lies within a range of a reference amplitude and/or phase respectively. An amplitude and/or phase counter may be incremented if the measured amplitude and/or phase lies outside the range of the reference amplitude and/or phase respectively. A confidence level value of a cyclic redundancy check (CRC) for at least a portion of the phase shift keyed section of the frame may be determined based on a determined value of the incremented amplitude and/or phase counter.

Abstract: A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down converted to base band frequencies and base band signals to be up converted to wideband RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning the LO frequency with the frequency of the received RF signals, signal power measuring circuitry for measuring the signal to signal and power ratio and for adjusting frontal and rear amplification stages accordingly, and finally, filtering circuitry to filter high and low frequency interfering signals including DC offset.

Abstract: A radio transceiver device includes circuitry for radiating electromagnetic signals at a very high radio frequency both through space, as well as through wave guides that are formed within a substrate material. In one embodiment, the substrate comprises a dielectric substrate formed within a board, for example, a printed circuit board. In another embodiment of the invention, the wave guide is formed within a die of an integrated circuit radio transceiver. A plurality of transceivers with different functionality is defined. Substrate transceivers are operable to transmit through the wave guides, while local transceivers are operable to produce very short range wireless transmissions through space. A third and final transceiver is a typical wireless transceiver for communication with remote (non-local to the device) transceivers.