Abstract: An apparatus, system, and method for assembling a ball grid array (BGA) package is described. A stiffener/heat spreader is provided. A substrate has a first surface and a second surface. The substrate has a central window-shaped aperture that extends through the substrate from the first substrate surface to the second substrate surface. The first substrate surface is attached to a surface of the stiffener/heat spreader. A portion of the stiffener/heat spreader is accessible through the central window-shaped aperture. An IC die has a first surface and a second surface. The first IC die surface is mounted to the accessible portion of the stiffener/heat spreader. A drop-in heat spreader has a surface that is mounted to the second IC die surface.

Abstract: A line driver for generating 10 BT signals is disclosed. Digital symbols to be transmitted via a 10 BT Ethernet line are converted by a digital-to-analog converter into a corresponding analog voltage signal, which is fed into an active output impedance line driver. The digital-to-analog converter also receives a reference voltage reflecting variations of the supply voltage and adjusts its output signal accordingly to provide a deliberately variable analog voltage signal to the line driver.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device and includes a WLAN interface, a transcoder, and a switch box. The WLAN interface wirelessly communicates with at least one WLAN device to receive inbound packetized audio data from the at least one WLAN device and to transmit outbound packetized audio data to the at least one WLAN device. The transcoder receives the inbound packetized audio data and converts the inbound packetized audio data to inbound Pulse Code Modulated (PCM) WLAN audio data. The WLAN interface also receives outbound PCM WLAN audio data and converts the outbound PCM WLAN audio data to the outbound packetized audio data. The switch box operably couples between the transcoder and a PCM bus, to which an audio COder/DECoder (CODEC) couples. A speaker and a microphone coupled to the audio CODEC.

Abstract: A method for designing an interpolation filter begins by partitioning interpolation filtering into a plurality of interpolation filtering stages that are cascaded together. Each of the plurality of interpolation filtering stages includes an up sampling stage and a filtering stage. The method continues by manipulating a first one of the interpolation filtering stages based on a first digital signal processing identity to produce a first equivalent interpolation filtering stage. The method continues by manipulating a second one of the interpolation filtering stages based on the first digital signal processing identity to produce a second equivalent interpolation filtering stage. The method continues by simplifying the first and second equivalent interpolation filtering stages to produce at least a simplified portion of the interpolation filter.

Abstract: According to the present invention, the multiple processor device determines routing for a plurality of data segments. In determining the routing, the multiple processor device first receives the plurality of data segments. The plurality of data segments include multiplexed data fragments from at least one of a plurality of virtual channels. Further, a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The multiple processor device then applies at least one routing rule to one of the plurality of data segments to produce at least one result corresponding to the one of the plurality of data segments. The multiple processor device then interprets the at least one result to determine whether sufficient information is available to render a routing decision for the one of the plurality of data segments.

Abstract: Methods and apparatus are provided for improving ARC4 processing in a cryptography engine. A multiple ported memory can be used to allow pipelined read and write access to values in memory. Coherency checking can be applied to provide that read-after-write and write-after-write consistency is maintained. Initialization of the memory can be improved with a reset feature occurring in a single cycle. Key shuffle and key stream generation can also be performed using a single core.

Abstract: A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats is disclosed. In particular, the system is able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations. The system includes carrier and timing recovery loops adapted to operate on an enhanced pilot signal as well as decision directed carrier phase recovery loops. Phase detectors operate on I and Q rail signals, or generate a Q rail from a Hilbert transform of the I rail. Decision directed loops incorporate a trellis decoder in order to operate on sequence estimated decisions for improved reliability in poor SNR environments.

Abstract: A system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In an embodiment of the present invention a two-level memory coherency scheme is implemented for use by multiple processors operably coupled to multiple buses in the same integrated circuit. A control device, such as node controller, is used to control traffic between the two coherency levels. In an embodiment of the invention the first level of coherency is implemented using a “snoopy” protocol and the second level of coherency is a directory-based coherency scheme.

Abstract: A home wireless router establishes a Wireless Local Area Network (WLAN) and services a plurality of wireless terminals within the WLAN service area including at least one Voice over Internet Protocol (VoIP) wireless terminal. The home wireless router receives a request from the VoIP wireless terminal to establish a VoIP conference call with at least two other VoIP wireless terminals. The home wireless router interacts with the VoIP service accumulator to determine at least one other home wireless router required to service the VoIP conference call, queries the at least one other home wireless router to determine its ability to service the VoIP conference call for at least one serviced VoIP wireless terminal, and receives a response from the at least one other home wireless router. The home wireless router, the at least one other home wireless router, and the VoIP service accumulator then set up and service the VoIP conference call.

Abstract: A system and method for controlling the delivery of power to a powered device in a Power over Ethernet Broad Reach (PoE-BR) application. Cabling power loss in a PoE-BR application is related to the resistance of the cable itself. A PHY can be designed to measure electrical characteristics (e.g., insertion loss, cross talk, length, etc.) of the Ethernet cable to enable determination of the cable resistance. The determined resistance in a broad reach cable can be used in increasing a power budget allocated to a power source equipment port.

Abstract: A method and system for a multi-rate Media Access Control layer (MAC) to Physical layer (PHY) interface is provided. The method to provide a multi-rate Media Access Control layer (MAC) interface comprises receiving a first set of signals, sampling the first set of signals to determine a type of interface to be used to transmit or receive the first set of signals or a subset of the first set of signals, generating a select signal indicating type of interface to be used based on the sampling step and transmitting the first set of signals or a subset of the first set of signals using the interface indicated by the select signal.

Abstract: A data scrambling circuit is provided. The data scrambling circuit includes an integrated circuit having a digital logic device and an interface circuit coupled to the digital logic device. Also included is an external memory coupled to output pins on the interface circuit. The digital logic device communicates patterned data to the interface circuit. The interface circuit then scrambles the patterned data to produce a pseudo random output to be stored within the external memory and unscrambled a pseudo random signal from the external memory to produce unscrambled data to be read by the digital logic device.

Abstract: Quadratic polynomial permutation (QPP) interleaver providing hardware saving and flexible granularity adaptable to any possible turbo code block size. A means is presented by which only a very small number of coefficients need be stored to effectuate a wide variety of QPP interleaves as can be employed in the context of turbo coding. In one instance, to accommodate the approximate 6000 different turbo code block sizes in 3GPP LTE channel coding, only 5 different coefficient values need to be stored to effectuate a very broad range of QPP interleaves to be applied each of those various turbo code block sizes. Moreover, a few small number of dummy bits, if any, need to be employed to accommodate a very broad range of turbo code block sizes. It is noted that the QPP interleaving as described herein can be applied to turbo encoding and turbo decoding (e.g., including both interleaving and de-interleaving).

Abstract: A system and method for discovering a cable type using an automated, systematic process. A PHY can be designed to measure electrical characteristics (e.g., insertion loss, cross talk, length, etc.) of the cable to enable determination of the cable type. The determined cable type can be used in diagnosis of cabling infrastructure or in a dynamic configuration or operation process.

Abstract: Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave. A means is presented by which any desired number of parallel implemented turbo decoding processors can be employed to perform turbo decoding that has been performed using a QPP interleave. This approach is presented to allow an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) to perform decoding of a turbo coded signal while still using a selected embodiment of a QPP interleave. In addition, a collision-free memory mapping, MOD,C,W) provides more freedom for selecting the particular quadratic polynomial permutation (QPP) interleave (?) that satisfies a parallel turbo decoding implementation with any desired number of parallel implemented turbo decoding processors.

Abstract: A method for transmitting wide bandwidth signals in a network that includes legacy devices begins by determining channel bandwidth of a channel that supports the wide bandwidth signals in the network. The method continues by determining overlap of legacy channel bandwidth with the channel bandwidth of the channel. The method continues by providing a legacy readable preamble section within the channel where the legacy channel bandwidth overlaps the channel bandwidth of the channel.

Abstract: Amplifying magnitude metric of received signals during iterative decoding of LDPC code and LDPC coded modulation. By appropriately selecting a metric coefficient value that is used to calculate the initial conditions when decoding LDPC coded signals, a significant reduction in BER may be achieved at certain SNRs. The appropriate selection of the metric coefficient value may be performed depending on the particular SNR at which a communication system is operating. By adjusting this metric coefficient value according to the given LDPC code, modulation, and noise variance, the overall performance of the decoding may be significantly improved. The convergence speed is slowed down so that the decoder will not go to the wrong codeword, and the moving range of the outputs of the decoder is restricted so that the output will not oscillate too much and will eventually move to the correct codeword.

Abstract: According to one exemplary embodiment, an inductor-tuned buffer circuit includes at least one input transistor for receiving a time varying input signal, where the at least one input transistor drives an output of the buffer circuit. The buffer circuit further includes a buffer inductor coupled to the output of the buffer circuit. The buffer circuit is utilized to drive a capacitive load through an interconnecting conductor, where the buffer inductor is situated in proximity to the capacitive load so as to cause a parasitic inductance of the interconnecting conductor to be less than, or much less than, the buffer inductor.

Abstract: A system and method for a generalized packet header suppression mechanism is described. This mechanism is implemented via a descriptor table. An exact copy of the descriptor table is stored in both the sender and receiver of packets via a communication medium. Entries in the descriptor table provide the information necessary to both suppress and expand the headers of well-known packets. The sender of the packet uses the descriptor table to suppress the packet header prior to transmitting the packet over the communication medium. When the packet reaches the receiver, the receiver uses the descriptor table to expand or reconstruct the packet header. This procedure results in less bandwidth required to transmit well-known messages because known header data is not transmitted via the medium, thereby not wasting bandwidth. The suppression mechanism allows the complete suppression of the header of a packet (as opposed to the traditional payload suppression) by a shorter message descriptor.

Abstract: Methods for improving communication performance in a wireless communication system where the wireless communication system has at least one mobile wireless communication device and a plurality of transmitter/receiver sites. The transmitter/receiver sites have a geographic area, defined as a cell, within which the mobile wireless communication devices can communicate with at least one of the transmitter/receiver sites. The methods determine when the mobile wireless communication device should rate shift or roam based on connection quality measurement data or position information such as GPS. In one method, the measurement data is subjected to configurable parameters to create a functional relationship value that is recorded. The recorded functional relationship values are trended and extrapolated to determine whether a rate shift or roam should be performed.