Abstract: A method determines RW head radial position relative to tracks within a magnetic data disc. This involves sensing both a S-burst signal and a P-burst signal with the RW head. The S-burst signal and P-burst signal are associated with a two-burst servo pattern on the magnetic disc. The S-burst pattern has a phase that remains constant radially across tracks within the magnetic disc. The P-burst has a second phase that rotates radially across tracks within the magnetic disc. By determining a phase difference between a sensed S-burst signal and P-burst signal, it is possible to determine the RW head radial position relative to the tracks on the magnetic disc.

Abstract: The modulation format of a data block (frame) received from a servicing base station by a wireless terminal in a cellular wireless communication system is identified. This involves first receiving several radio frequency (RF) bursts of one data block (frame) from the servicing base station. The RF burst carries a number of modulated symbols. The training sequence is extracted from the RF burst and is made of a number of modulated symbols. The training sequences are first processed assuming a first modulation format to produce a first accumulated channel energy. Then, the training sequences are processed assuming a second modulation format to produce a second accumulated channel energy. The first and second accumulated channel energies are compared to determine which accumulated channel energy is greater. The modulation format of the data block is identified as the modulation format corresponding to the greater accumulated channel energy.

Abstract: An electrically and mechanically enhanced die-down tape substrate ball grid array (BGA) package substrate is described. An IC package includes a substrate that has a first surface. The first surface has a central opening. A stiffener/heat spreader has a first surface. The first surface of the stiffener has a central ground ring. The first surface of the stiffener is coupled to a second surface of the substrate. The central opening has an edge. The edge includes at least one of the following: (a) a protruding edge portion that extends across at least a portion of the central ground ring, (b) a recessed edge portion that exposes a portion of the central ground ring, or (c) a hole proximate to the edge, wherein the hole exposes a portion of the central ground ring.

Abstract: A receiver circuit of the modem is coupled to receive a continuous analog signal from a communication channel. This analog signal includes both packet and idle information. A burst mode protocol is also provided, in which packets of digital information are modulated by a transmitter circuit of the modem, thereby converting the packets of digital information into analog signal bursts of discrete duration. These analog signal bursts are transmitted from the transmitter circuit to a telephone line. A receiver circuit monitors the telephone line to detect the analog signal bursts. Upon detecting the presence of the analog signal bursts on the telephone line, the receiver circuit demodulates the analog signal bursts using full processing capabilities of the receiver circuit. However, upon detecting the absence of the analog signal bursts on the telephone line, the demodulating function of the receiver circuit is disabled.

Abstract: A wireless network card includes an adaptable antenna connection structure that includes connections for one or more internal antennas and for one or more Radio Frequency (RF) connectors that may be coupled to one or more external antennas. A Printed Circuit Board (PCB) and electronic components located thereon form the wireless network card. The PCB includes a removable portion that, when removed, leaves an opening that receives an RF antenna connector. When the PCB is used to create a client wireless network card, one or more surface mount antennas are mounted on the PCB and coupled to surface mount antenna conductive pads formed thereon. The wireless network card may include (1) the surface mount antenna; (2) the RF connector; or (3) both the surface mount antenna and the RF connector.

Abstract: A channel select filter having channel equalization includes a first low pass filter stage, a gain stage, a subtraction module, and a second low pass filter stage. The first low pass filter stage is operably coupled to filter input signals to produce first low pass filtered signals. The gain stage is operably coupled to adjust gain of the input signals to produce gained input signals. The subtraction module is operably coupled to subtract the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage is operably coupled to filter the first stage signals to produce channel selected signals.

Abstract: Segregation of redundant control bits in an ECC permuted, systematic modulation code. Appropriately encoding of user information via combined modulation and RS (Reed-Solomon) encoding ensures segregation of scrambled user information, modulation redundancy bits, and RS redundancy bits in such a way that each of the components thereof can be segregated and stored within any desirable digital information memory storage device. By providing this segregated capability, when accessing a portion of a RS codeword from the memory, an entire RS codeword need not be read from the memory. In fact, only the particular field (or bits) needs to be accessed to perform correction thereon. This segregation provides for a reduction in the hardware complexity of translation between user information and a modulation codeword. Also, this segregation provides for the ability to perform correction of only one of the scrambled user information, the modulation redundancy bits, or the RS redundancy bits.

Abstract: A home network, in one embodiment including a home wiring system; a demarcation point unit in electrical communication with the home wiring system; and a home network module in electrical communication with the home wiring system. The home network module is adapted for connection to a home electronic device. The demarcation point unit passes data to and receives data from the home electronic device through the home network module.

Abstract: A system and method of analyzing a powered device (PD) in a Power-over-Ethernet (PoE) system are presented. The system includes an Ethernet interface having a physical layer (PHY) chip capable of providing a signal pulse in addition to physical layer 1 functions. The system further includes a pulse transformer, coupled to the PHY chip, capable of relaying the signal pulse provided by the PHY chip to the PD via the transmit line and a second PHY chip. The first PHY chip receives one or more return pulse signals from the PD, analyzes characteristics such as voltage and/or frequency of the return pulse signal(s), and determines attributes of the PD based on those characteristics. The attributes can include powered device validity and power classification. A method of supplying power to a PD is also presented.

Abstract: An integrated circuit radio transceiver and method therefor is operable to determine a transmit scheme according to an ordered manner. More specifically, the system is operable to determine a transmit scheme that defines a signaling configuration that includes number of spatial streams, antenna configuration information, code rate, quadrature modulation type, and transmission protocol modulation scheme, transmitting a packet according to the transmit scheme and collecting packet error rate success and failure information of ongoing data transmissions.

Abstract: An integrated circuit radio transceiver and associated method comprises a multi-mode device operable to support personal area network communications as well as traditional wireless local area network communications. In one embodiment, IEEE 802.11 protocol IBSS communications are used to transport Bluetooth communication data packets. Thus, the multi-mode device is operable to establish traditional BSS communications with an Access Point in addition to establishing peer-to-peer communications with another multi-mode device to transport the Bluetooth communications over the 802.11 IBSS communication link.

Abstract: An integrated circuit radio transceiver and associated method comprises a multi-mode device operable to support personal area network communications as well as traditional wireless local area network communications. In one embodiment, IEEE 802.11 protocol IBSS communications are used to transport Bluetooth communication data packets. In another embodiment, a direct link comprising direct packet transfers without beaconing is performed between the multi-mode device and another multi-mode device. Thus, the multi-mode device is operable to establish traditional BSS communications with an Access Point in addition to establishing peer-to-peer communications with another multi-mode device to transport the Bluetooth communications over the 802.11 IBSS communication link or over an IEEE 802.11 direct communication link.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: A balun that includes a first conductor, a second conductor, and a third conductor. The first conductor has a first length. The first conductor also has a first end connected to a first balanced power amplifier output port. The second conductor has substantially the same first length. The second conductor also includes a first end connected to a second balanced power amplifier output port and a second end connected to a second end of the first conductor. The third conductor has substantially the same first length. The third conductor has a first end connected to an antenna port and a second end connected to a ground potential.

Abstract: An integrated circuit radio transceiver and associated method comprises a multi-mode device operable to support personal area network communications as well as traditional wireless local area network communications. In one embodiment, IEEE 802.11 protocol IBSS communications are used to transport Bluetooth communication data packets. In another embodiment, a direct link comprising direct packet transfers without beaconing is performed between the multi-mode device and another multi-mode device. Thus, the multi-mode device is operable to establish traditional BSS communications with an Access Point in addition to establishing peer-to-peer communications with another multi-mode device to transport the Bluetooth communications over the 802.11 IBSS communication link or over an IEEE 802.11 direct communication link.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: A Galois field multiplier array includes a 1st register, a 2nd register, a 3rd register, and a plurality of multiplier cells. The 1st register stores bits of a 1st operand. The 2nd register stores bits of a 2nd operand. The 3rd register stores bits of a generating polynomial that corresponds to one of a plurality of applications (e.g., FEC, CRC, Reed Solomon, et cetera). The plurality of multiplier cells is arranged in rows and columns. Each of the multiplier cells outputs a sum and a product and each cell includes five inputs. The 1st input receives a preceding cell's multiply output, the 2nd input receives at least one bit of the 2nd operand, the 3rd input receives a preceding cell's sum output, a 4th input receives at least one bit of the generating polynomial, and the 5th input receives a feedback term from a preceding cell in a preceding row. The multiplier cells in the 1st row have the 1st input, 3rd input, and 5th input set to corresponding initialization values in accordance with the 2nd operand.

Abstract: A communication system includes a link module having a first serial interface for interfacing to a serial link. The link module also including a second serial interface. The system also includes a Media Access Control (MAC) module including a parallel interface. The system also includes a converter module, coupled between the parallel interface and the second serial interface, configured to convert symbols, transferred between the parallel interface and the second serial interface, between a parallel format at the parallel interface and a serial format at the serial interface.

Abstract: A method of parameter estimation in a shared channel communications system includes the steps of receiving a preamble including a first sequence corresponding to a sequence having zero autocorrelation, a second sequence having zero autocorrelation, and a third sequence having zero autocorrelation, performing a coarse carrier frequency estimate based on the first sequence, and performing a fine carrier frequency estimate based on the second and third sequences.