Abstract: Methods and systems for monitoring operating status of a device are provided. Aspects of the method may include receiving within a chip, a signal indicative of a power information of an on-chip device. An output signal indicative of the power information may be generated from within the chip, while the chip is operating. The generated output signal may be communicated outside the chip via a serial bus, a plurality of pin connections on said chip, and/or a general purpose input/output connection. The generated output signal may be multiplexed on at least one pin on the chip and it may comprise a clock signal and/or a data signal. The data signal may comprise sequential power information for a plurality of on-chip devices.

Abstract: Aspects of the present invention may include replicating a first primary packet to create a second primary packet for a particular channel. A unique identifier may be assigned to the first primary packet and a different unique identifier may be assigned to the second primary packet. The first primary packet may be replicated in order to create a first secondary packet and the second primary packet may be replicated to create a second secondary packet. In response to the receipt of the new stream with replicated packets, the first or said second primary packet may be selected and the first or second secondary packet may be selected for a particular PID based on the assigned unique identifier. The selections may be done to co-relate the selected first and/or second primary packet with a legacy system or the selected first and/or second secondary packet with a new system.

Abstract: A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate and in a natural order. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines.

Abstract: The present invention relates to a design of a computer system that processes instructions with a specific operation code causing the processor to execute a certain operation twice and a method for running such computer system in a time and register space saving manner. A method is provided for executing at least one computer instruction which defines at least a first source operand and an operation to be carried out on the operand, the instruction containing at least one address field of a predetermined bit length and at least one repeated execution bit related to the first operand. The method includes accessing the first source operand; accessing the repeated execution bit and deriving from that repeated execution bit a repeated execution code defining a repeated execution condition; and selectively carrying out the operation defined in the instruction once, twice or more times in dependence of the repeated execution code.

Abstract: A method for calibrating a filter begins with the filter filtering a first signal having a first frequency to produce a first filtered signal, wherein the first frequency is in a known pass region of the filter. The processing continues by measuring signal strength of the first filtered signal to produce a first measured signal strength. The processing continues with the filter filtering a second signal having a second frequency to produce a second filtered signal, wherein the second frequency is at a desired corner frequency of the filter. The processing continues by measuring signal strength of the second filtered signal to produce a second measured signal strength. The processing continues by comparing the first measured signal strength with the second measured signal strength to determine whether the filter has attenuated the second signal by a desired attenuation value with respect to the first signal.

Abstract: A multiple processor device stores a stream of data as a plurality of data segments, which includes multiplexed data fragments from at least one of a plurality of virtual channels. The data segments that comprise the stream of data correspond to the multiplexed data fragments from the virtual channels. The multiple processor device then decodes at least one data segment in accordance with one of a plurality of transmission protocols to produce a decoded data segment. The multiple processor device then stores the decoded data segment to align it in accordance with a data path segment size. The multiple processor device then interprets the stored decoded data segment with respect to a corresponding one of the plurality of virtual channels to determine a destination of the stored decoded data segment. The multiple processor device then stores the decoded data segment as part of reassembled data.

Abstract: A network switch having at least one port data port interface, a first memory, a second memory, and a memory management unit in connection with the at least one data port interface, the first memory, and the second memory. The memory management unit operates to receive data from the at least one data port interface, determine if the data is to be stored in one of the first memory or the second memory, store the data in one of the first memory or the second memory as a linked list, retrieve the data from one of the first memory or the second memory, and forwards the data for egress.

Abstract: A first primary packet to create a second primary packet for a particular PID. Different CRC checksum may be generated for the first and the second primary packet. The first primary packet may be replicated in order to create a first secondary packet and the second primary packet may be replicated to create a second secondary packet. The CRC checksum for the primary packets may be stored within their corresponding secondary packets. In response to receipt of a new stream with replicated packets, the first or said second primary packet may be selected and the first or second secondary packet may be selected for a particular PID based on the generated CRC checksum. The selections may co-relate the selected first and/or second primary packet with a legacy system or the selected first and/or second secondary packet with a new system.

Abstract: A method for payload-based channel estimation of a wireless channel begins by receiving a frame via the wireless communication channel. The frame includes a training sequence, a frame information section, and a plurality of time sequential data payload sections. As the frame is being received, the method continues by determining a channel estimation based on the training sequence. The method continues as the frame is being received by determining a channel estimation of a data payload section of the plurality of time sequential data payload sections to produce a payload channel estimation. The method continues as the frame is being received by updating the channel estimation based on the payload channel estimation to produce an updated channel estimation.

Abstract: Aspects of the invention may comprise receiving an incoming TCP packet at a TEEC and processing at least a portion of the incoming packet once by the TEEC without having to do any reassembly and/or retransmission by the TEEC. At least a portion of the incoming TCP packet may be buffered in at least one internal elastic buffer of the TEEC. The internal elastic buffer may comprise a receive internal elastic buffer and/or a transmit internal elastic buffer. Accordingly, at least a portion of the incoming TCP packet may be buffered in the receive internal elastic buffer. At least a portion of the processed incoming packet may be placed in a portion of a host memory for processing by a host processor or CPU. Furthermore, at least a portion of the processed incoming TCP packet may be DMA transferred to a portion of the host memory.

Abstract: A DC compensation circuit restores the frequency spectrum of an input signal at DC (or 0 Hz) by removing or reducing DC offset, 1/f noise, or any other unwanted noise at or near 0 Hz. The DC compensation is performed using direct coupling, as opposed to AC coupling, so that no useful signal information in the active period of the input signal is lost at DC. The DC compensation circuit samples the input signal during an inactive period of the input signal. Afterwhich, the unwanted DC noise is determined from the sampled signal and stored until an active period of the input signal. For example, the sampled signal can be filtered using a passband around DC so as to isolate the signal energy at DC during the inactive period. Since there is no useful signal information present during the inactive period, any signal energy at the output of the filter is necessarily unwanted DC noise.

Abstract: A radio frequency identification (RFID) decoding subsystem includes a pre-decode module and a decode module. The pre-decode module is coupled to process down-converted RFID signals into at least one of pre-decoded baseband data and corresponding decoding information. The decode module is coupled to process the pre-decoded baseband data into decoded RFID data, where the processing of the pre-decoded baseband data is based on the corresponding decoding information when the corresponding decoding information is produced by the pre-decoder module.

Abstract: A method and related computer program product for combining resources of multiple RAID controllers and managing them as a single entity, comprising searching the RAID controllers for the most appropriate version of the firmware to be executed, determining whether a more appropriate version of the firmware was previously loaded into system memory, unloading inappropriate versions of the firmware, loading the most appropriate version of the firmware and initializing all RAID controllers as a commonly managed entity having combined resources.

Abstract: An apparatus for transmitting data in an xDSL system is disclosed. In an exemplary embodiment, the apparatus comprises a transmitter that sends data over an xDSL system in the form of a data transmission unit (DTU), the transmitter having physical media specific—transmission convergence (PMS-TC) communication sublayer. The apparatus may further include a retransmission unit that is implemented in the PMS-TC sublayer. The retransmission unit may include a retransmission buffer that stores and indexes transmitted DTUs in retransmit containers. The retransmit container may be defined as a time slot corresponding to a sent DTU, wherein the retransmission unit is configured to respond to a retransmission request indicating which stored DTU should be retransmitted. The stored DTU to be retransmitted may be identified by its corresponding retransmit container.

Abstract: A method and system for communicating data in an xDSL data retransmission mode is disclosed. A data transmission unit (DTU) is defined. The DTU is sent in an xDSL data stream. A retransmit container is further defined a as a time slot that corresponds to a sent DTU. A copy of the sent DTUs and an index of corresponding retransmit containers is maintained. The DTUs are transmitted the in the xDSL data stream. A determination is made on whether a transmitted DTU was corrupted during transmission. Each corrupted DTU is identified by its corresponding retransmit container. An uncorrupted copy of the DTU is then retransmitted as identified by the corresponding retransmit container.

Abstract: LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics.

Abstract: Systems and methods that provide graphics using a graphical engine are provided. In one example, a system may provide layered graphics in a video environment. The system may include a bus, a graphical engine and a graphical pipeline. The graphical engine may be coupled to the bus and may be adapted to composite a plurality of graphical layers into a composite graphical layer. The graphical engine may include a memory that stores the composite graphical layer. The graphical pipeline may be coupled to the bus and may be adapted to transport the composite graphical layer.

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

Abstract: A node includes a processor coupled to an interconnect and a memory bridge coupled to the interconnect. The processor is configured to maintain a first indication of whether or not a modification of data at a first address has been detected by the processor after a most recent load-linked (LL) instruction was executed by the processor to the first address. The memory bridge is responsible for internode coherency within the node, and is configured to initiate a first transaction on the interconnect in response to receiving a probe command from another node. The processor is configured, during a time period in which the processor has a second transaction outstanding to the first address, to change the first indication to the first state responsive to the first transaction.

Abstract: A system, method, and apparatus for reducing the video decoder processing requirements for rewinding a HITS stream are presented herein. During rewind of a HITS stream, the video decoder builds a clean reference picture. The clean reference picture is built by decoding each of the P-pictures in the EP-EP segment. However, because the P-pictures are not displayed, the decoder does not decode the portion of the P-picture below the last intracoded slice. The decoder can build the clean reference picture without decoding the portions of the P-pictures below the last intracoded slice because the subsequent pictures do not use the said portions for prediction.