Abstract: A wireless network in a communication infrastructure has a packet switched backbone network and includes a plurality of access points and services a plurality of client devices. The plurality of access points communicatively coupled to the packet switched backbone network and each have access point processing circuitry and access point wireless transceiver circuitry. The plurality of client devices each have client processing circuitry and client wireless transceiver circuitry. A client device of the plurality of client devices, using respective client processing circuitry and respective client wireless transceiver circuitry, determines interference parameters regarding wirelessly communicating within the wireless network. The client device then transmits the interference parameters to an access point of the plurality of access points.

Abstract: The present invention provides a modular headset operable to support both voice communications and voice activated commands. This may involve the use of multiple voice CODECs to process voice communications and voice activated commands. The modular headset includes both a microphone and wireless earpiece. The earpiece may further include an interface, a processing circuit, a speaker, a user interface, a pairing circuit, and a registration circuit. The interface allows the earpiece to communicate with the base unit that couples the modular headset to a servicing network. This coupling to the servicing network and base unit only occurs when the headset is successfully registered to the base unit. The pairing circuit and registration circuit allow the exchange of pairing or registration information between various components. The pairing circuit allows the wireless earpiece and microphone to exchange pairing information which is then compared to determine whether or not a successful pairing can be achieved.

Abstract: A system and method for automatically tuning timing of a signal (e.g., a data timing signal) utilizing determined delay of a variable delay element and for utilizing such a tuned signal. Various aspects of the invention may comprise experimentally determining delay characteristics of an on-chip variable delay circuit utilizing an on-chip test module. A delay control signal for an on-chip variable delay circuit may be determined based at least in part on the experimentally determined delay characteristics. Timing of a signal may be adjusted by inputting the signal and the delay control signal into the on-chip variable delay circuit. The time-adjusted signal may then be utilized in signal processing. Such signal processing may, for example, comprise receiving an input data timing signal, generating a delayed input data timing signal, and generating an output data timing signal based on the input data timing signal and the delayed input data timing signal.

Abstract: An RSSI circuit provides a relatively inexpensive technique for accurately measuring received signal strength over a wide dynamic range. A received signal is processed by a rectifier circuit that generates a series of DC offsets of increasing magnitude. The DC offsets are imposed on a first polarity of the received signal to create a series of outputs that are the first polarity of the received signal with increasing DC offsets. Each of the outputs is coupled to one input of a weighted comparator with the other input of the comparator coupled to a second and opposite polarity of the received signal with no offset. The comparators determine when overlap occurs to indicate particular signal levels.

Abstract: Methods and systems for correlation sharpening filtering of a composite video signal are provided. A correlation between a current pixel and at least one adjacent pixel may be determined. A plurality of chroma video signal components of a composite video signal may be blended based on the determined correlation. A luma video signal component may be determined based on the blended chroma video signal components. At least a portion of the plurality of chroma video signal components may be filtered, resulting in filtered chroma video signals. At least a portion of the plurality of chroma video signal components may be blended with the filtered chroma video signal based on the determined correlation. The blended at least a portion of the plurality of chroma video signal components may be removed from the composite video signal to obtain the luma video signal component.

Abstract: Certain embodiments of the invention may be found in a method and system for automatic aspect ratio detection and may comprise scanning lines in at least a selected portion of an image and locating a first reference pixel in one of the scanned lines. A corresponding sliding sum and a sliding number may be generated starting from the first reference pixel and a white edge determined based on the generated sliding sum and/or the generated sliding number. The first reference pixel may be a non-black pixel and a value which corresponds to and defines non-black may be variably defined. The sliding sum and the sliding number may utilize m bins, where m is greater than one (1). A luma sum threshold may be compared with the generated sliding sum to locate the white edge for aspect ratio detection.

Abstract: A plurality of System On a Chip (SOC) integrated circuits, a media that intercouples the plurality of SOC integrated circuits to form at least one SOC LAN ring, and a routing address scheme. Each SOC integrated circuit includes at least one processor, a system bus, a memory controller, at least two Local Area Network (LAN) ports, and a receive channel selection block. The media intercouples the LAN ports of the plurality of SOC integrated circuits to form at least one SOC LAN ring. The routing address scheme serves in routing of data packets on the at least one SOC LAN ring. A routing address of the routing address scheme has a first portion that identifies a source SOC integrated circuit, a second portion that identifies a destination SOC integrated circuit, and a third portion that comprises a LAN address and data.

Abstract: System and method for integrating communications between two switches. The system includes a first switch, a second switch and a CPU. The first switch has a first plurality of ports, and the second switch has a second plurality of ports. The CPU is coupled to the first switch and the second switch, and is configured to control and program the first and second switch. A port of the first plurality of ports, as a first link port, is coupled to a port of the second plurality of ports, as a second link port. The first plurality of ports are designated by a first numbering scheme, the second plurality of ports are designated by a second numbering scheme, and the first and second link ports each have a tag insertion unit, a processing unit and a removing unit, for inserting an inter-stack tag, processing the packet, and removing the inter-stack tag.

Abstract: A system and method for matching chip and package terminals and for packaging integrated circuits. Various aspects of the present invention may comprise receiving as input a first list of chip terminal identifiers and a second list of package terminal identifiers. The first and second lists may be analyzed with a first string-matching algorithm to determine a first set of matching pairs of chip terminals and package terminals. The first and second lists may also be analyzed with a second string-matching algorithm to determine a second set of matching pairs of chip terminals and package terminals. The first and second sets of matching pairs may be compared to identify common matching pairs between the first and second sets of matching pairs. An indication of the common matching pairs may then be output.

Abstract: A node comprises one or more resources and a register programmable with an indication during use. The one or more resources are addressed with addresses within a local region of an address space. The indication identifies a second region of the address space that is aliased to the local region, and other nodes address the one or more resources using addresses in the second region.

Abstract: A method is presented that monitors the quality of a communications channel. The method includes receiving a data signal and establishing a zero reference phase of the received data signal. The method further includes generating a phase-shifted data signal by phase shifting the received data signal relative to the zero reference phase, and sampling the phase-shifted data signal for one or more phase-shift positions. A zero reference phase is reestablished between sampling at each of the phase-shift positions. The method also includes detecting bit errors in the phase-shifted data signal at each of the phase-shift positions in order to provide a communications channel quality measurement. In an embodiment, the method includes generating an eye diagram according to a count of detected bit errors relative to a count of detected bits. The eye diagram characterizes the quality of the communications channel.

Abstract: Tracing instruction flow in an integrated processor by defeaturing a cache hit into a cache miss to allow an instruction fetch to be made visible on a bus, which instruction would not have been made visible on the bus had the instruction fetch hit in the cache. The defeature activation is controlled by use of a defeature hit signal bit in a defeature register, and in which the bit may be programmed.

Abstract: An ATM network traffic shaper is implemented in hardware. The traffic shaper shapes transmit data on one or more virtual circuits (VCs) according to the specified quality of service (QoS) parameters. Thus, the traffic shaper provides for the delivery of associated data cells in accordance with the specified QoS parameters. The traffic shaper is scalable in that the number of supported VCs can be increased with a relatively small increase in the size of the device and associated logic gates. The traffic shaper supports constant bit rate (CBR), variable bit rate (VBR), and unknown bit rate (UBR) service types and generates cell transmit requests with zero cell delay variation (CDVT). The traffic shaper also provides very high resolution in terms of bit rate specification. Varying shaping resolutions are achieved by varying a shaping interval time (SIT) generated by a SIT counter.

Abstract: A phase locked loop includes a detection module, a control conversion module, a controlled oscillation module, a divider module, and a power distribution module. The detection module is operably coupled to produce a difference signal based on a difference between a reference oscillation and a feedback oscillation. The control conversion module is operably coupled to convert the difference signal into a control signal. The controlled oscillation module is operably coupled to produce an output oscillation based on the control signal. The divider module is operably coupled to produce the feedback oscillation based on the output oscillation. The power distribution module is operably coupled to receive a supply voltage and to provide an individual supply voltage to at least one of the detection module, the control conversion module, the controlled oscillation module, and the divider module to optimize at least one of performance and power consumption of the phase locked loop.

Abstract: A method for synchronizing clocks in a packet transport network. The method comprises, receiving an external network clock at a central packet network node and transmitting timing information to a plurality of packet network devices, the timing information based upon the external network clock. The method further comprises, transmitting and receiving data that is synchronized to the timing information to a plurality of connected packet network devices. And finally, delivery of packets to an external interface via a packet network that contains data synchronized to the external network clock.

Abstract: Methods and systems for time constant for a 3D comb filter of a video signal are provided. Aspects of the method may include assigning a weight to a 3D comb mesh value. Combing may be blended according to the assigned weight of the 3D comb mesh value. The weighted 3D comb mesh value may be accumulated in order to generate accumulated mesh value. If the accumulated mesh value exceeds a saturation value, the accumulated mesh value may be reduced to the saturation value. If the 3D comb mesh value is smaller than a first threshold value, the accumulated mesh value may be reset to zero. A multiplier may be generated according to the accumulated mesh value. If the accumulated mesh value is between a second threshold value and a third threshold value, the multiplier may be blended.

Abstract: Method and system for translating Verilog to C++ are provided herein. Aspects of the method for translating may include searching for a Verilog pattern in a Verilog file and substituting the Verilog pattern with a C++ language expression, wherein the C++ language expression is associated with the same functionality as the Verilog pattern. It may be identified whether the Verilog file comprises at least one of a task library, a main driver, and a driver module. If the Verilog file comprises a task library, a Verilog task within the task library may be identified; and the Verilog task may be translated into a C++ function. If the Verilog file comprises a main driver, a C++ interface header may be inserted in the Verilog file.

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract: A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.