Abstract: A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to determine equalizer coefficients for a composite signal that includes a first information signal and a second information signal. First and second information signal channel estimates and channel powers based upon training symbols are determined. A composite signal power is determined. A noise variance of the composite signal is determined based upon the first information signal channel power, the second information signal channel power, and the composite signal power. A plurality of equalizer coefficients are determined based upon the first information signal channel estimate, the second information signal channel estimate, and the noise variance of the composite signal.

Abstract: A cable modem includes a cable transceiver, coupled to a wide area network via a cable network, that operates operating in accordance with a first wired communication protocol. A first radio frequency (RF) transceiver provides a first remote device bidirectional broadband access to the wide area network via a first short range radio frequency link operating at a first selected carrier frequency. A programmable antenna is dynamically tuned to the first selected carrier frequency to transmit and receive an RF signal over the first short range radio frequency link.

Abstract: A baseband processing module of a Radio Frequency receiver produces time domain equalizer coefficients and calculates a power threshold based upon a total power of a plurality of taps of the time domain equalizer coefficients. The baseband processing module then performs a plurality of iterations, during each of which it identifies at least one minimum power tap and determines a total power figure based upon zeroing the at least one minimum power tap. When the total power figure compares favorably to the power threshold, the baseband processing module modifies the plurality of taps by zeroing the at least one minimum power tap and continuing iterating. When the total power figure compares unfavorably to the power threshold, the baseband processing module ceases iterating without modifying the plurality of taps by zeroing the at least one minimum power tap and then produces modified time domain equalizer coefficients.

Abstract: A system for processing radio frequency (RF) signals includes a searcher and a plurality of Cluster Path Processor (CPPs). The searcher detects a maximum signal energy level and position of at least one of a plurality of individual distinct path signals in a signal cluster of a first information signal, wherein at least a portion of the plurality of individual distinct path signals is received within a duration of a corresponding delay spread. The sampling position is used as a starting sampling location by the plurality of CPPs, including a first information signal CPP and a second information signal CPP. Fine sampling positions of the plurality of CPPs are based upon channel energy estimates for the plurality of individual distinct path signals. CPP outputs are employed to produce channel estimates, which are themselves used in subsequent equalization operations. Sampling positions may change over time in order to satisfy alignment criteria.

Abstract: A circuit and method to reduce jitter and/or noise in a phase-locked loop (PLL). A voltage-controlled oscillator (VCO) control signal is tapped and filtered to create a low-noise, filtered VCO control signal. The filtered and unfiltered control signals are individually weighted and then combined to create a modified VCO control signal which reduces the jitter and/or the noise by reducing an effect of VCO gain on the jitter and/or the noise.

Abstract: An RF transmission system includes a plurality of RF transmitters that generate a plurality of RF signals at a selected carrier frequency in response to a frequency selection signal. A plurality of programmable antennas are each tuned to the selected carrier frequency, in response to the frequency selection signal, to transmit a corresponding one of the plurality of RF signals.

Abstract: A radio frequency identification (RFID) system includes a network RFID reader, an RFID tag, and an RFID reader. The network RFID reader is coupled to a network connection. The RFID tag is coupled to generate an RFID response signal in response to an RFID signal. The RFID reader is coupled to provide the RFID signal to the RFID tag and to provide the RFID response signal to the network RFID reader.

Abstract: A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to receive a time domain signal that includes time domain training symbols and time domain data symbols. The baseband processing module includes a channel estimator operable to process the time domain training symbols to produce a time domain channel estimate, a Fast Fourier Transformer operable to convert the time domain channel estimate to the frequency domain to produce a frequency domain channel estimate, a weight calculator operable to produce frequency domain equalizer coefficients based upon the frequency domain channel estimate, an Inverse Fast Fourier Transformer operable to converting the frequency domain equalizer coefficients to the time domain to produce time domain equalizer coefficients, and an equalizer operable to equalize the time domain data symbols using the time domain equalizer coefficients.

Abstract: A multiple band antenna structure includes a plurality of antenna sections and a coupling circuit. The coupling circuit is operable in a first mode to couple the plurality of antenna sections into a first antenna structure for transceiving radio frequency signals within a first radio frequency band and is operable in a second mode to couple the plurality of antenna sections into a second antenna structure for transceiving radio frequency signals within a second radio frequency band, where each of the plurality of antenna sections is tuned to a corresponding frequency band.

Abstract: An integrated circuit includes a baseband processing module, an RF section, and an interface module. The baseband processing module converts an outbound voice signal into an outbound voice symbol stream; converts an inbound voice symbol stream into an inbound voice signal; converts outbound data into an outbound data symbol stream; converts an inbound data symbol stream into inbound data; converts outbound image/video data into an outbound image/video symbol stream; and converts an inbound image/video symbol stream into inbound image/video data.

Abstract: A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to receive a time domain signal that includes desired signal and interfering signal time domain training symbols and time domain data symbols.

Abstract: A system for processing radio frequency (RF) signals includes a searcher and a Cluster Path Processor (CPP). The searcher detects a maximum signal energy level and position of at least one of a plurality of individual distinct path signals in a signal cluster, wherein at least a portion of the plurality of individual distinct path signals is received within a duration of a corresponding delay spread. The CPP includes a group finger array having a plurality of group fingers and determines a coarse sampling position of the group finger array based upon the position of the at least one of a plurality of individual distinct path signals in the signal cluster. The CPP determines a fine sampling position based upon determines a composite channel energy estimate for the plurality of individual distinct path signals. Using this fine sampling position, the CPP receives at least a portion of the plurality of individual distinct path signals by the group finger array.

Abstract: An RFIC includes a transmit acoustic transducer, a digital conversion module, a transmit baseband module, an analog conversion module, an up-conversion module, a power amplifier circuit, a low noise amplifier circuit, a down-conversion module, a receive baseband processing module, and a receive acoustic transducer circuit. The transmit acoustic transducer circuit converts transmit sound waves into transmit electrical signals. The digital conversion module converts the transmit electrical signals into digital transmit audio signals and converts down-converted signals into digital receive baseband or low IF signals. The transmit baseband processing module converts the digital transmit audio signals into digital transmit baseband or low IF signals. The analog conversion module converts the digital transmit baseband or low IF signals into analog transmit baseband or low IF signals and converts digital receive audio signals into receive electrical signals.

Abstract: A (radio frequency) RF transmission system includes an RF transmitter that generates an RF signal at a sequence of selected carrier frequencies. A frequency hop module, coupled to the RF transmitter generates the sequence of selected carrier frequencies. A programmable antenna is tuned to each of the sequence of selected carrier frequencies to transmit the RF signal via an antenna current.

Abstract: A Radio Frequency (RF) transceiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to receive a time domain signal that includes time domain training symbols and time domain data symbols. The baseband processing module processes the time domain training symbols to produce a time domain channel estimate, Fast Fourier Transformer operations that convert the time domain channel estimate to the frequency domain to produce a frequency domain channel estimate, weight calculation operations that produce frequency domain equalizer coefficients based upon the frequency domain channel estimate, Inverse Fast Fourier Transformer operations that convert the frequency domain equalizer coefficients to the time domain to produce time domain equalizer coefficients, and equalization operations that equalize the time domain data symbols using the time domain equalizer coefficients.

Abstract: A bit stream demultiplexer that couples a high-speed bit stream media to a communication Application Specific Integrated Circuit (ASIC). The bit stream multiplexer performs its demultiplexing function staged within at least two integrated circuits. The first Integrated Circuit (IC) receives a first bit stream and performs a first demultiplexing function. A second IC performs a second demultiplexing function. The second IC acts as either a slave or a master to the first IC. In a slave mode, the second IC depends upon a transmit data clock from the first IC for latching bit stream data received from the first IC. When the second IC operates in the master mode, the second IC uses the transmit data clock from first IC as a reference input for a PLL to generate a Receive Data Clock. If an LOL or LOS occurs within the first IC, a signal to the second IC indicates these conditions causing the second IC to switch to a local oscillator reference clock to generate the Receive Data Clock.

Abstract: In a video system, a method and system for pixel constellation in a motion detection deinterlacer are provided. An output pixel in an absent line of a current frame may be determined based on a constellation of pixels from at least one present line above and at least one present line below the absent line. The present lines may be immediately above and/or below the absent line. Pixels from the present lines immediately above and/or below include the pixel directly above and/or below the output pixel and/or at least two pixels to either side. The output pixel may also be determined from present lines in fields that occur prior to and/or after the current field. The fields may be those that occur immediately before and/or after the current field and/or the second and third field that occur after the current field.

Abstract: Presented herein is a scheme for processing multilayered packets. In one embodiment, an application engine aligns a lower level packet header with data objects in the multilayered packet. Additionally, the memory stores the objects of the multilayered packet, such that the objects start at the beginning of a data word. Remainder portions of data words can store 0's. Additionally, an object table stores records comprising object identifiers associated with particular objects, and the address where the particular object is stored.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Provided are a method and system for removing an offset direct current (DC) component from an input waveform. The method includes multiplying the input waveform with a demodulation waveform to produce a first differential current signal. An absolute value representation of the demodulation waveform is multiplied with a reference DC offset value to produce a second differential current signal. The first and second differential current signals are then differenced.