Abstract: General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes. A novel means is presented in which contention-free memory mapping is truly achieved in the context of performing parallel decoding of a turbo coded signal. A novel means of performing the contention-free memory mapping is provided to ensure that any one turbo decoder (of a group of parallel arranged turbo decoders) accesses only memory (of a group of parallel arranged memories) at any given time. In doing so, access conflicts between the turbo decoders and the memories are avoided.

Abstract: Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size. A novel means is presented by which any desired turbo code block size can be employed when only requiring, in only some instances, a very small number of dummy bits. This approach also is directly adaptable to parallel turbo decoding, in which any desired degree of parallelism can be employed. Alternatively, as few as one turbo decoder can be employed in a fully non-parallel implementation as well. Also, this approach allows for storage of a reduced number of parameters to accommodate a wide variety of interleaves.

Abstract: In a video system, a method and system for minimizing both on-chip memory size and peak DRAM bandwidth requirements for multi-field deinterlacers are provided. Present line pixels and absent line pixels may be determined and may be ordered into upper line pixels and lower line pixels based on whether an interlaced output frame is top field or bottom field originated. Upper line pixels may be buffered in an upper line FIFO that may hold half a video line and lower line pixels may be buffered in an lower line FIFO that may hold a video line. A source switch and a line length counter may be used to assemble the deinterlaced output frame by selecting from the buffered upper line pixels and the buffered lower line pixels. The deinterlaced output frame may be buffered in an output FIFO.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Mapping of m input bits to 2m modulation symbols of a two-dimensional symbol constellation. A quarter-quadrant constellation of 2m-4 modulation symbols that are located in a first quadrant of the two-dimensional signal plane is formed with each modulation symbol associated with a respective m-4 bit label. A quarter constellation of the two-dimensional symbol constellation is formed by adding to the quarter-quadrant constellation three copies of the quarter-quadrant constellation rotated by ?90 degrees, 180 degrees, and ?270 degrees, respectively, and then displacing the quarter constellation by a shift value ?, with each modulation symbol associated with a respective m-2 bit label. The two-dimensional symbol constellation is then formed by adding to the quarter constellation three copies of the quarter constellation rotated by +90 degrees, 180 degrees, and +270 degrees, respectively. Each symbol of the two dimensional constellation is associated with a respective m bit label of the m input bits.

Abstract: One embodiment of the present invention uses an abbreviated blanking period, in comparison to the standard VESA and CEA-EIA blanking periods, in order to send data, including low bandwidth, non-timing information, over one or more channels of the digital video link. By shortening the blanking period, the amount of time available for sending data in each scan line is increased, enabling the system to send more data over each channel. The inactive video portion of a scan line sent during vertical sync may also be used to send additional digital data. Shortening the blanking periods and/or using the inactive video sections of the horizontal scan lines adds to the overall data capacity of the link and may be used to send other digital data, such as multi-channel audio, video, control, timing, closed captioning or other digital data.

Abstract: A method and apparatus are disclosed to aid a transceiver chip, in a serial data communications system, in recovering from a system-side, out-bound data clocking problem. If a problem with a primary clock signal, used to clock data from a system-side of a transceiver chip through at least a part of an out-bound data path of the transceiver chip, is detected, then a more reliable secondary clock signal is substituted for the primary clock signal. Once it is determined that the primary clock signal has recovered, the primary clock signal is switched back to and certain discrete circuits of the out-bound data path of the transceiver chip are automatically reset in hardware without the need for system level intervention to avoid any problems due to clock glitches on the primary clock signal during the switching.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: An improved directional coupler that significantly reduces the signal degradation problems associated with distortion caused by circuit elements used to measure the transmitted power. In a selected embodiment, the directional coupler of the present invention comprises a plurality of active elements, such as capacitors, that have values selected to ensure that the distortion created by circuit elements used to measure forward transmitted power. In an embodiment of the invention, capacitors have values selected to minimize in-band distortion signals at the fundamental carrier frequency of the transmitted signal and also at the second and third harmonics of the fundamental carrier frequency.

Abstract: Local oscillation circuitry for use in an RF transceiver Integrated Circuit (IC) includes local oscillation generation circuitry operable to produce a local oscillation and local oscillation distribution circuitry. The local oscillation distribution circuitry includes a splitting circuit, a first distribution portion, and a second distribution portion. The splitting circuit receives the local oscillation and produces multiple copies of the local oscillation. The first distribution portion produces a first local oscillation corresponding to a first RF band and a second local oscillation corresponding to a second RF band based and to provide the first local oscillation and the second local oscillation to a first RF transceiver group. The second distribution portion produces a first local oscillation and a second local oscillation and provides the first local oscillation and the second local oscillation to the second RF transceiver group.

Abstract: A data switch for network communications includes a data port interface which supports at least one data port which transmits and receives data. The switch also includes a CPU interface, where the CPU interface is configured to communicate with a CPU, and a memory management unit, including a memory interface for communicating data from the data port interface to the switch memory. A communication channel is also provided, communicating data and messaging information between the data port interface, the CPU interface, the switch memory, and the memory management unit. The data port interface also includes an access control unit that filters the data coming into the data port interface and takes selective action on the data by applying a set of filter rules such that access to the switch is controlled by the set of filter rules.

Abstract: A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port Serdes transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. The ring structure of the bus provides efficient communication between the logic core and the various data ports.

Abstract: Methods and apparatus for generating clocks for a handheld multistandard communication system are disclosed herein and may comprise receiving an input clock signal from a clock source whose accuracy is controlled by a selected device in a handheld multistandard communication system. The selected device may be characterized with a highest accuracy requirement among a plurality of devices. A main clock signal for at least one of the plurality of devices may be generated utilizing the received input clock signal. The generated main clock signal may be supplied to the plurality of devices within the handheld multistandard communication system in response to receiving a request from one of the plurality of devices. A real-time clock signal may be generated for low-power mode operation of the devices. The real-time clock signal may be generated by a real-time clock signal source and may be supplied to each device.

Abstract: Methods, systems and computer program products for global address space management are described herein. A System on Chip (SOC) unit configured for a global address space is provided. The SOC includes an on-chip memory, a first controller and a second controller. The first controller is enabled to decode addresses that map to memory locations in the on-chip memory and the second controller is enabled to decode addresses that map to memory locations in an off-chip memory.

Abstract: Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

Abstract: Methods, systems and computer program products to maintain cache coherency in a System On Chip (SOC) which is part of a distributed shared memory system are described. A local SOC unit that includes a local controller and an on-chip memory is provided. In response to receiving a request from a remote controller of a remote SOC to access a memory location, the local controller determines whether the local SOC has exclusive ownership of the requested memory location, sends data from the memory location if the local SOC has exclusive ownership of the memory location and stores an entry in the on-chip memory that identifies the remote SOC as having requested data from the memory location. The entry specifies whether the request from the remote SOC is for exclusive ownership of the memory location. The entry also includes a field that identifies the remote SOC as the requester. The requested memory location may be external or internal to the local SOC unit.

Abstract: According to an example embodiment, a method may include determining an actual location (N) of a burst error in a data block; selecting a burst error pattern that is a correctable error based on adjusting an error pattern syndrome by an adjustment amount (S); and determining a correction vector based on the burst error pattern; shifting the correction vector by an offset amount based on (N) and (S); and correcting the burst error in the data block based on the shifted correction vector.

Abstract: Global Positioning System (GPS) route creation via server interaction or wireless terminal collection creates a GPS route data file that includes starting location GPS coordinates, ending location GPS coordinates, and at least one way point location data element. Each way point location data element includes respective way point location GPS coordinates and a respective link to a corresponding digital photograph data file. Wireless terminals having corresponding sensors collect local meteorological conditions that are associated with digital photographs and GPS coordinates at capture. The digital photographs, GPS coordinates at capture, and local meteorological conditions are used to produce local weather reports for requesting client terminals. Virtual tours could also be conducted using the captured digital photograph files.

Abstract: Methods, systems and computer program products to communicate between System On Chip (SOC) units in a cluster configuration are provided herein. A local SOC unit that includes a local controller and a local on-chip memory is provided. In response to receiving a signal from a remote SOC, the local controller is configured to retrieve a message from a remote on-chip memory of the remote SOC and store the message in the local on-chip memory. The local controller is a node controller and the local on-chip memory is a Static Random Access Memory (SRAM). The local SOC and the remote SOC are part of a cluster.

Abstract: Method for streaming data over a plurality of data links formed between a Bluetooth® master device and a plurality of Bluetooth® slave devices includes constructing a vendor specific command host controller interface (HCI) packet, sending the vendor specific command HCI packet to a host controller of the Bluetooth® master device, and constructing at least one baseband packet addressed to each slave device of the plurality of slave devices. The vendor specific command HCI packet includes a plurality of ACL headers, a plurality of L2CAP headers, and a payload. A Bluetooth®-enabled device configured to stream data over a plurality of data links formed between a plurality of slave devices includes a Bluetooth®-enabled host adapted to construct a vendor specific command host controller interface (HCI) packet, an HCI transport layer and a host controller adapted to receive the vendor specific command HCI packet over the HCI transport layer.