Abstract: A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting a gain of the signal. At least one differential pair in each stage is permanently enabled. The variable gain amplifier may include a plurality of cascaded stages including the stage. In addition, the variable gain amplifier may be adjusted through an interleaved thermometer coding method.

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The method includes identifying a phase control signal from an adjacent current cell preceding the particular current cell in time and logically ORing the phase control signal from the preceding cell with a phase control signal from the particular current cell.

Abstract: Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the register memory. The plurality of operands may be one or more contiguous regions. The contiguous regions may be specified as an address and a format such as a row, a column, or a neighborhood relative to the address.

Abstract: A multi-level power amplifier architecture using a multi-tap transformer implemented on a single CMOS integrated circuit wireless communications device is described. By providing a multi-tap transformer for coupling a plurality of power amplifiers to a shared output impedance, such as an antenna, power transmission may be made at different levels while maintaining efficiency. With a multi-tap transformer having “N” taps featuring “N” different impedance levels, each tap may be connected to an amplifier cell which delivers power into the transformer at the tap for coupling to the output load. Any one of the “N” amplifier cells can be turned on at once along with any combination of the “N” amplifier cells.

Abstract: An apparatus and for enabling functionality of a component, wherein the apparatus includes an identification module having an identification number stored therein, and a hash function module in communication with the identification module. A host is provided and is in communication with the identification module, and a guess register in communication with the host is provided. An encryption module is provided and is in communication with the guess register, and a public key module in communication with the encryption module is provided, wherein the public key module has a public key stored therein. A comparator in communication with the encryption module and the hash function module is provided, such that the comparator may compare a first bit string to a second bit string to generate a function enable output for the component.

Abstract: The present invention establishes a communications link between a central office (CO) modem and a customer premise equipment (CPE) modem. The CO modem then evaluates the performance of the communications link. Impairments on the communications link are identified based on the evaluation results. Next, adjustment parameters for improving the performance of the communications link are determined. The CPE modem is then modified in accordance with the determined adjustment parameters to establish an adjusted communications link between the CO modem and the CPE modem. In this way, impairments such as bridged taps and cross-talk can be avoided.

Abstract: An amplifier circuit including a first transistor and a biasing circuit. The biasing circuit includes a process compensation circuit. The biasing circuit being coupled to a gate of the first transistor. A method for biasing an amplifier circuit is also included.

Abstract: A system for synchronizing configuration information in a plurality of data processing devices using a common system interconnect bus. The present invention provides a method and apparatus for enforcing automatic updates to the configuration registers in various agents in the data processing system. A node controller is operably connected to a system interconnect bus and a switch. A plurality of interface agents are connected to the switch, with each of the interface agents comprising a configuration space register, a configuration space shadow register and a control and status register (CSR). A token ring connected to the node controller is operable to transmit data from the node controller to a plurality of interface agents connected to the token ring, thereby providing a system for updating the various configuration registers in each of the agents.

Abstract: A wireless network card includes an adaptable antenna connection structure that includes connections for one or more internal antennas and for one or more Radio Frequency (RF) connectors that may be coupled to one or more external antennas. A Printed Circuit Board (PCB) and electronic components located thereon form the wireless network card. The PCB includes a removable portion that, when removed, leaves an opening that receives an RF antenna connector. When the PCB is used to create a client wireless network card, one or more surface mount antennas are mounted on the PCB and coupled to surface mount antenna conductive pads formed thereon. The wireless network card may include (1) the surface mount antenna; (2) the RF connector; or (3) both the surface mount antenna and the RF connector.

Abstract: An improved high-fanin multiplexer that is highly-scalable, fast and area-efficient. In one embodiment of the present invention, multiple logic “legs” are attached to a common output line. Each leg comprises one pMOS pull-up transistor and one nMOS pull-down transistor. The gate of the pMOS transistor in each leg is connected to the output of an And-Or-Invert (AOI) gate whose inputs are connected to a plurality of select lines and a plurality of data lines. The gate of the nMOS transistor in each leg is connected to the output of an Or-And-Invert (OAI) gate whose inputs are connected to a plurality of select lines (the logical complements of the select lines for the AOI), and a plurality of data input lines. The high-fanin multiplexer of the present invention offers numerous advantages over the prior art. In particular, the high-fanin multiplexer of the present invention has very small self-loading allowing a large number of inputs while also maintaining a high fan out speed.

Abstract: A wide gain range current digital-to-analog converter (DAC) is presented that includes a unit current cell having a current source module biased by a current source voltage bias, a differential switch module, a main cascode module biased by a first bias voltage and an attenuation cascode module biased by a second bias voltage, configured such that a particular current gain range is obtained at the main cascode module output when a unit current cell current is at or above a current threshold. The output current at the attenuation cascode module output can be input into a current attenuator when the unit current cell current is below the current threshold to obtain additional current gain range. The current attenuator can include a plurality of attenuator cells that can be programmed to a desired level of current gain in linear decibels or linear step intervals. Smaller step sizes can be obtained by programming a current source within the step intervals.

Abstract: Determination of a received signal strength indication in a direct conversion receiver begins by determining, at a given time, a 1st value to be the larger of the in-phase component of the received signal and the quadrature component of the received signal. The direct conversion receiver then determines a 2nd value at the given time to be the smaller of the in-phase component of the received signal and the quadrature component of the received signal. As such, at a given time, the 1st and 2nd values correspond to the greater and lesser of the in-phase component and quadrature component, respectively. Having obtained these values, the direct conversion receiver then determines the received signal strength indication based on the 1st value, the 2nd value and an offset value. The offset value provides a scaling of the RSSI value based on the range of the RSSI values.

Abstract: The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate.

Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A tuned transformer balun circuit includes a transformer balun, a first tuning capacitor, a second tuning capacitor, and a third tuning capacitor. A first plate of the first tuning capacitor is operably coupled to a first node of the differential winding and a second plate of the first tuning capacitor is operably coupled to a circuit ground. A first plate of the tuning capacitor is operably coupled to a second node of the differential winding and a second plate of the second tuning capacitor is operably coupled to the circuit ground. A first plate of the third tuning capacitor is operably coupled to a first node of the single-end winding and the second plate of the third tuning capacitor is operably coupled to transceiver radio frequency signals, wherein, based on loading of the single-ended winding and the differential winding, the first, second, and third tuning capacitors resonate with the transformer balun to provide efficient energy transfer from the transmitter section to the antenna.

Abstract: A scalable multi-power integrated circuit package for integrated circuits having spaced apart first, second and third pluralities of respective spaced apart chip power bonding pads connected to-corresponding first, second, and third chip power supply nets, the chip power bonding pads disposed adjacent to a chip periphery defining the chip area, the scalable multi-power integrated circuit package comprising: a central chip mounting area for mounting one of said integrated circuits, said chip mounting area defining a chip mounting area periphery surrounding said chip mounting area; spaced apart first, second and third package power supply continuous conductive traces, each trace disposed adjacent to the chip area mounting periphery; corresponding first, second and third pluralities of spaced apart package bonding areas defined along each respective one of said first, second and third package power supply continuous conductive traces, each respective one of said package bonding areas disposed in bondable alignme

Abstract: A method and computer program product for providing RTP suppression across a DOCSIS network. An index number and a set of rules are sent to a receiver. The index number indicates the type of header suppression technique (i.e., RTP header suppression) to be performed, and the set of rules define how to recreate the RTP packets on the receiving end. At least one complete RTP packet is transmitted upstream for enabling a receiver to learn the RTP header. Subsequent RTP packets are transmitted upstream for reconstruction at the receiving end. The subsequent RTP packets are comprised of delta values representing fields that dynamically change from packet to packet in an RTP header.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: A circuit includes a plurality of circuit components formed on a semi conductive substrate die and a bond wire. The plurality of circuit components include at least one active component that operates on an information signal, a tuning node coupled to the at least one active component, an Electro Static Discharge (ESD) protection inductor, and a chip pad. The chip pad couples to the tuning node. The ESD protection inductor communicatively couples between the tuning node and a rail formed on the semi conductive substrate die. The ESD protection inductor provides ESD protection prior to packaging of the semi conductive substrate die or in some cases prior to the installation of the packaged die on a PC board or the equivalent. The bond wire couples between the chip pad and a package pad and serves as a tuning inductor for the circuit.