Abstract: A network device for monitoring a memory partitioned by an identifier can include at least one port configured to receive at least one packet. The at least one packet includes an identifier relating to priority of the at least one packet. The network device can also include a buffer memory having at least one buffer configured to store the at least one packet, and a counter configured to modify a counter value therein when the buffer memory is accessed with respect to the at least one data packet, wherein the counter corresponds to the identifier with respect to the at least one packet.

Abstract: The network device includes a transceiver, a pattern generation unit and a pattern recognition unit. The transceiver connects to a communications medium. The pattern generation unit connects to the transceiver. The pattern generation unit is configured to generate a first code word in response to a self-test signal. The pattern recognition unit connects to the communications medium and a network entity. The pattern recognition unit is configured to receive the first code word from the transceiver and to determine whether the first code word includes a loop back pattern. The pattern recognition unit is configured to generate a second code based upon the first code word and to include in the second code word a pattern different from the first code word.

Abstract: A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming portion of an integrated circuit to operate at a relatively higher average clock rate than a more power consuming portion operating at a relatively lower clock rate, by adjusting the duration of the cycles of the higher frequency clock. The adjustment may be according to the supply voltage changes that result from logic switching activity of the more power consuming portion, and may be performed in a manner that substantially matches the delay behavior of the logic. The phase of the higher frequency clock remains locked to the lower frequency clock. An embodiment of the present invention may reduce the area and cost of an integrated circuit by minimizing the need for other on-chip power supply noise mitigation approaches, while also improving device throughput and performance.

Abstract: Methods and systems for protecting integrated circuits from power-on sequence currents and for biasing transistors in paths susceptible to power-on sequence damage are provided. The system includes a plurality of protection circuits coupled between a first circuit input and a second circuit input. Each protection circuit includes a switch and a voltage sensors. When the voltage amplitude of a first voltage source coupled to the protection circuit exceeds a first threshold and the voltage amplitude of a second voltage source coupled to the protection circuit is below a second threshold, the switch is closed, coupling the first circuit input to the second circuit input. When the voltage amplitude of the first voltage source exceeds the first threshold and the voltage amplitude of the second voltage source exceeds the second threshold, the switch is open, decoupling the first circuit input from the second circuit input.

Abstract: The present invention finds the optimum organization of compiled code within an application to ensure maximal cache efficiency. A configuration file specifies predefined cache, optimization, and application parameters. The cache parameters include a cache size, cache line size, set associativity, address-to-cache-line mapping algorithm, and set replacement algorithm. The optimization parameters specify the minimum acceptable efficiency level. The application parameters include a list of object modules and functions within those modules. All possible orderings of the modules are stepped through to determine where the specified functions fall within the cache given the location of the function within the module. The function locations in each permutation of the orderings are analyzed to find a solution that matches or beats the optimization parameters. In an embodiment, a front-end analysis program (“tool”) and a back-end processing stage, usually related to a linker, are provided.

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract: A stacked MOS configuration for use in short channel length analog circuit technologies is provided. The stacked MOS configuration comprises a plurality of short-channel MOS transistors coupled in series and sharing a common gate terminal. In an embodiment, a first peripheral transistor provides a drain terminal for the stacked MOS configuration. A second peripheral transistor provides a source terminal for the stacked MOS configuration. Adjacent transistors in the stacked MOS configuration are connected in a drain-to-source configuration.

Abstract: A radio frequency (RF) phase shifter having an RC-CR circuit that includes a first capacitor having a first capacitor node and a second capacitor node and a first resistor coupled between the first capacitor node and a ground. The RC-CR circuit also includes a second resistor having a first resistor node and a second resistor node and a second capacitor coupled between the first resistor node and the ground. The RF phase shifter generates arbitrary phase shift by using a scheme of adding two perpendicular vectors with variable gains (or amplitudes).

Abstract: A method and apparatus are provided for enabling a transmitter to have a substantially linear magnitude response and a substantially linear phase response. The transmitter includes first and second power amplifier drivers (PADs) having respective first and second non-linear phase responses. The first non-linear phase response is based on a first bias applied to the first PAD, and the second non-linear phase response is based on a second bias applied to the second PAD. The first and second PADs are coupled in parallel to provide a combined substantially linear phase response. According to an embodiment, the first and second PADs have respective first and second average input capacitances. Signal swings about the first and second biases vary the respective first and second average input capacitances, which may be combined to provide a combined average input capacitance that is substantially insensitive to the signal swings about the first and second biases.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A sample and hold circuit including a plurality of input signal sampling switches using native NMOS transistors in combination with switched bulk PMOS transistors. The input signal sampling switches input a differential input signal and output an intermediate differential signal. A plurality of capacitors are connected to the intermediate differential signal. A plurality of summing junction switches receive charge stored on the plurality of capacitors, and output a differential sampled and held charge to the summing junction. The plurality of input signal sampling switches include first, second, third, and fourth switches each having an input and an output. Inputs of the first and third switches are connected to a first voltage of the differential input voltage. Inputs of the second and fourth switches are connected to a second voltage of the differential input voltage. Outputs of the first and second switches are connected together and to an input of a first capacitor of the plurality of capacitors.

Abstract: A circuit is formed to steer current in and out of an inductive load in a manner that enables an amplifier to provide a plurality of gain steps without modifying an LC time constant for the circuit and, therefore, without modifying the tuning or frequency of oscillation for the circuit. A first group of MOSFETs are coupled in parallel and define the circuit current flow. A second group of MOSFETs are coupled in parallel to each other and in series to an impedance device. A third group of MOSFETs coupled to steer current in and out of the impedance device to affect the output signal coupled to one end of the impedance device. The transistors in the second and third groups of MOSFETs are selectively activated to control the amount of current that goes through the impedance device.

Abstract: A versatile data handling apparatus providing multiple alternatives for inputting data is disclosed. The apparatus includes an array of depressible keys, a screen-based input system that is located distinctly from the depressible keys, an optical information sensing component and a visual display to present visual information to a user. The data input activities are coordinated by a computerized data handling system communicatively coupled with the various components.

Abstract: The input stage of the fully differential amplifier output stage is configured in a differential pair configuration with a tail current. The tail current is divided between two legs of the input stage and is higher in the leg that has the higher of the two input voltage levels (in or inb). The devices in each leg of the fully differential amplifier output stage may be cascoded to avoid electrical voltage overstress. The top device in each leg of the differential input stage may be coupled in a diode configuration and is utilized to mirror the current into another NMOS current mirror as well as to a PMOS output device. The gate of the PMOS output devices are connected in a cross-coupled configuration. The NMOS current mirrors are utilized to mirror the current into the NMOS output devices in a non-cross-coupled configuration.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: A radio transceiver includes circuitry that enables received RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a temperature sensing module that produce accurate voltage level readings may be mapped into corresponding temperature values. A processor, among other actions, adjusts gain level settings based upon detected temperature values. One aspect of the present invention further includes repetitively inverting voltage signals across a pair of semiconductor devices beings used as temperature sensors to remove a common mode signal to produce an actual temperature-voltage curve. In one embodiment of the invention, the circuitry further includes a pair of amplifiers to facilitate setting a slope of the voltage-temperature curve.

Abstract: The wide bandwidth transceiver includes a receiver section, a transmitter section, and a local oscillation module. The receiver section includes a 1st receiver intermediate frequency (IF) stage, a receiver switch module, and a 2nd receiver IF stage. The 1st receiver IF stage is operably coupled to convert a 1st inbound radio frequency (RF) signal into a 1st inbound IF signal based on a 1st local oscillation of the local oscillation module. The receiver switch module passes either the 1st inbound IF signal or a 2nd inbound RF signal, which have similar carrier frequencies, to the 2nd receiver IF stage. The 2nd receiver IF stage receives the selected signal from the receiver switch module and based on a 2nd local oscillation converts the selected signal into a low intermediate frequency signal. The transmitter section includes a 1st transmitter intermediate frequency (IF) stage, a 2nd transmitter IF stage, a power amplifier and a transmitter switch module.

Abstract: A shared memory packet switching device includes: a shared memory providing a shared memory space; an input logic unit associated with at least one receive port, and being operative to determine whether the associated receive port is saturated by determining whether a number of packets received via the associated receive port and currently stored in the shared memory exceeds a drop threshold value; a packet routing control unit operative to determine a destination one of the transmit ports for each of the received data packets; and an output logic unit associated with at least one of the transmit ports, the output logic unit being communicatively coupled with the packet routing control unit, and being operative to determine whether the associated transmit port is congested by determining whether a number of packets currently stored in the shared memory that are to be transmitted via the associated transit port exceeds a congestion threshold value, and also being operative to generate an associated output full

Abstract: A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a headend and a plurality of cable modems located different distances from the headend. The power transmission level, slot timing, and equalization of the cable modems are set by a ranging process. Data is transmitted by the modems in fragmented form. Various measures are taken to make transmission from the cable modems robust. The upstream data transmission is controlled to permit multiple access from the cable modems.

Abstract: A high-speed CMOS transmit/receive antenna switch includes a first transistor, a second transistor and a parasitic compensation network. The first transistor is operably coupled to an antenna, to a transmit path, and to receive a transmit/receive (T/R) control signal. The second transistor is operably coupled to the antenna, the receive path, and to receive the T/R control signal. When the T/R control signal is in a first state, the first transistor is active and the second transistor is inactive such that the transmit path is coupled to the antenna. When the T/R control signal is in a second state, the second transistor is active and the first transistor is inactive such that the receive path is coupled to the antenna. The parasitic compensation network is coupled to compensate for adverse effects of parasitic components of the first and second transistors at operating frequencies of the transmit/receive antenna switch.