Abstract: In a communications system (such as cable modem communications), dynamic payload header suppression (DPHS) is applied to a data stream to reduce header overhead. DPHS allows the suppression of static fields as well as fields that change in a predictable manner (i.e., predictably dynamic fields). To suppress predictably dynamic fields, delta encoding is utilized to enable a cable modem to replace a dynamic field with information indicating how the field is different from the same field in a previous packet in the data stream. DPHS constructs a suppression mask by using a special packet called a “learn” packet. The “learn” packet is a copy of the original packet with extra bytes that guide the suppression process. It indicates that both the sending and receiving entities are to take a full copy of a packet header, which is then used as a reference to reconstruct the suppressed fields.

Abstract: A method of handling data packets in a series of network switches includes receiving an incoming data packet at a data port of a first switch of the series of network switches. A module id bitmap of the incoming data packet is resolved and a bit corresponding to the first switch of the module id bitmap is examined to determine if the bit is set. A destination address of the incoming data packet is resolved when the corresponding bit is set and the incoming data packet is forwarded or dropped based on the destination address. When the corresponding bit is not set, the incoming data packet is forwarded to a next switch of the series of network switches. A network switch configured to allow for cascading of data packets is also disclosed.

Abstract: Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.

Abstract: A reduced state maximum likelihood sequence estimator allows the use of improved equalization techniques that provides greatly improved performance for channels with severe attenuation and spectral nulls. The reduced state maximum likelihood sequence estimator retains kn states of a total number of K states, kn<K, with each retained state having an associated state metric. (J)(kn) new states are determined based on kn previous states and a most recently received sample, using J transitions, J being a less than L, where L is a size of a symbol alphabet. (J)(kn) new state metrics are determined which are respectively associated with each new state. The new state metrics are compared to a threshold and those states whose metric does not exceed the threshold are retained. The reduced complexity of the MLSE allows for the use of partial response equalizers, e.g., a partial response class V (PRV) equalizer.

Abstract: Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. A novel approach is presented for variable modulation encoding of LDPC coded symbols. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and/or modulation signal whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis.

Abstract: A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal. The transconductance stage includes a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a second MOS transistor having a second gate oxide thickness and a second channel length.

Abstract: A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a headend and a plurality of cable modems located different distances from the headend. The power transmission level, slot timing, and equalization of the cable modems are set by a ranging process. Data is transmitted by the modems in fragmented form. Various measures are taken to make transmission from the cable modems robust. The upstream data transmission is controlled to permit multiple access from the cable modems.

Abstract: A method of preventing Hot Carrier Injection in input/output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can tolerate. By placing input/output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. A circuit for preventing Hot Carrier Injection in these input/output devices comprises comparing an input voltage to a reference voltage, and if conditions that would produce Hot Carrier Injection are present (e.g. when input voltage is greater than reference voltage), slowing the turn-on of one of the series connected input/output devices, thereby reducing the voltage from the drain-to-source of another series connected input/output device.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Abstract: Characterizing channel response in a single upstream burst using redundant information from training tones (TTs). The invention is operable to utilize inserted TTs, contained within a transmitted data frame, to provide for an improved estimate of a communication channel's actual response and an improved estimate of the noise of the communication channel. The invention determines a maximum allowable delay spread of the many communication paths within a multi-path communication channel. Using the redundant TTs information, then a portion of the finite impulse response of the communication channel, within the time domain, may be zeroed, thereby providing a much improved channel estimate and noise estimate. Using the redundant TTs, less noise is introduced onto the data tones (DTs) within a data frame. The present invention is also able to identify those portions of the TTs that are attributable to the actual channel and those that are attributable to the channel's noise.

Abstract: Embodiments of the present invention perform logical operations utilizing a symmetric logic circuit comprising two logic units. In a symmetric logic circuit, the circuit configuration used to process a first logic input in the first logic unit is the same as the circuit configuration used to process a second logic input in the second logic unit, and the circuit configuration used to process the second logic input in the first logic unit is the same as the circuit configuration used to process the first logic input in the second logic unit. The present invention may be used for logic circuits that perform a variety of logical operations, such as XOR, AND, NAND, OR, or NOR.

Abstract: Iterative data-aided carrier CFO estimation for CDMA systems. Any communication receiver may be adapted to perform the iterative data-aided carrier CFO estimation. The iterative data-aided carrier CFO estimation is performed using a high accuracy method. The operation may be described as follows: a received signal is despread and buffered. Using the received preamble sequence, an initial estimate of the CFO is obtained. This estimate is used to correct the whole despread data. The corrected data using the initial CFO estimate is sliced. Each despread data symbol is divided by the corresponding sliced data decision. The obtained sequence is then averaged across different codes to obtain a less noisy sequence, which is then used to estimate the CFO again. The procedure can be repeated (iterated) to obtain a more accurate carrier frequency offset estimate; the number of times in which the procedure is repeated may be programmable or predetermined.

Abstract: In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the combined adder and incrementer circuits embodying the invention also provides an output indicating whether a CarryOut signal resulted from the incrementing operation, or whether the CarryOut signal resulted from the addition. The preferred embodiments utilize prefix-type adder circuits using a single carry chain. Alternate embodiments generate a CarryOut signal as a function of the incrementing operation, using either generate and propagate signals or from generate and kill signals from the carry chain.

Abstract: A method and apparatus are disclosed for enhancing the pipeline instruction transfer and execution performance of a computer architecture by reducing instruction stalls due to branch and jump instructions. Trace cache within a computer architecture is used to receive computer instructions at a first rate and to store the computer instructions as traces of instructions. An instruction execution pipeline is also provided to receive, decode, and execute the computer instructions at a second rate that is less than the first rate. A mux is also provided between the trace cache and the instruction execution pipeline to select a next instruction to be loaded into the instruction execution pipeline from the trace cache based, in part, on a branch result fed back to the mux from the instruction execution pipeline.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Optimal decision metric approximation in bit-soft decisions. The present invention provides for calculation of the decision metrics/branch metrics for determining whether an incoming analog signal should be transformed into a 1 or a 0 in the digital realm. In performing these decisions, there is some probability associated with the decision to map the incoming signal to a value of 1 or 0. These decisions made in extracting bits from a particular symbol are typically referred to as bit-soft decisions. In making these bit-soft decisions, decoders commonly use decision metrics/branch metrics as mentioned above. Whereas prior art approaches typically are very computationally intensive to calculate these values, the present invention provides for a much improved and simplified calculation of decision metrics/branch metrics that may be used in bit-soft decisions. The optimal metric approximation may be implemented using a few mathematical operations and simple comparison logic circuitry.

Abstract: A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on.

Abstract: Modified branch metrics for processing bit-soft decisions to account for phase noise impact on cluster variance (CV). The present invention is able to partition a modulation scheme's constellation into two or more regions, so that the bit-soft decision branch metrics may be adjusted based on the CV of the various constellation points. A confidence level may be attached to the various constellation points based on their particular CVs. There are a number of methods to ascertain the CV of the constellation's points, including finding characteristics of various components in a communication system (transmitter, communication channel and receiver), and any method may be used within various embodiments. The modification of the branch metrics/confidence level may be performed in a communication receiver; the communication receiver may be implemented in a communication system employing the vector orthogonal frequency division multiplexing (VOFDM) portion of the broadband wireless internet forum (BWIF).

Abstract: A memory management unit (MMU) for a network switch fabric for forwarding data is disclosed. The MMU has an ingress port interface receiving portions of a data packet and an egress port interface, connected to ingress ports of the fabric through an ingress bus ring. The MMU also includes a cell packer, that groups packet data into cells and a packet pool memory, that stores cells received from the cell packer. The MMU also includes a cell unpacker, where the cell unpacker separates stored cells before releasing the cells to an egress port. The MMU also includes an egress scheduler communicating with the cell unpacker, where the egress scheduler determines which packet data should be retrieved from the packet pool memory according to priority rules. The priority rules can be a deficit round robin scheduling algorithm or a weighted round robin scheduling algorithm.