Abstract: A method of controlling a delay-locked loop (DLL) module is disclosed. The method includes the steps of receiving a clock signal, comparing the received clock signal with a reference clock signal to determine whether a required phase difference between the signals is within specified tolerances, producing a correction signal when the required phase difference between the received clock and reference clock signals is not within the specified tolerances, utilizing the correction signal to change a delay setting and forwarding the correction signal to slave DLL modules in communication with the DLL module. The comparing, producing, utilizing and forwarding steps are performed only after a period of time has elapsed from a prior incidence of the comparing, producing, utilizing and forwarding steps, where the period of time is sufficient to allow the DLL to settle and no extraneous results are produced.

Abstract: Decoding time stamps (DTSs) and presentation time stamps (PTSs) are used in fine granularity scalability (FGS) coding during MPEG-4 video coding. An input video is encoded in an FGS encoder into a base layer bitstream and an enhancement bitstream. The bitstreams are provided over a variable bandwidth channel to an FGS decoder. The DTSs and the PTSs are selected during encoding as to conserve memory during FGS decoding. The video object planes (VOP) in the bitstreams include base VOPs and FGS VOPs, and may also include fine granularity temporal scalability (FGST) VOPs. The FGS VOPs and the FGST VOPs may be organized in the same layer or in different layers. The base VOPs are combined with the FGS VOPs and the FGST VOPs to generate enhanced VOPs.

Abstract: A voltage regulator may include one or more features for generating high PSRR. For example, source follower devices may be included in the voltage regulator for providing current sources for the output voltage nodes. The source followers may be sensitive to power supply noise at the gate terminal. Filters are included on the gate terminals to filter the power supply noise, thus reducing the noise at the gate terminals. As another example, the voltage regulator may employ current sources on the output voltage nodes which produce current inversely proportional to the current drawn by the load. In one embodiment, the voltage regulator may include a power control circuit used to provide overvoltage protection during power up. The power control circuit provides a voltage during power up, and ceases providing the voltage after a time interval so that the circuit may operate.

Abstract: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0?, x1?} such that a number of 1's at bit x0? over time is within ?1 of a number of 1's at bit x1?. At least two 4-bit vector shufflers input the vectors {x0?, x1?}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0?, x1?} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0?, x1?} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

Abstract: A Multi-tone transmission system processes input data through a plurality of intermediate processing stages 12,14,16 and corresponding stages of intermediate data 18,20. A symbol including a number of tones is obtained therefrom by an inverse Fourier transform 24 and stored in a buffer 158. The peak amplitude that the symbol would contain after the subsequent processing in the analogue front end 146 is modelled and compared with a threshold. If the modelled peak amplitude in the symbol exceeds the threshold, the symbol stored in the buffer 158 is regenerated. The symbols stored in the buffer are output through the analogue front end 146.

Abstract: A signal strength indicator circuit that includes a first amplifier configured to receive a first input signal from a first mixer and a second input signal from a second mixer;. The circuit also includes a second amplifier configured to receive a first set of differential inputs from the first amplifier. The circuit further includes a third amplifier configured to receive a second set of differential inputs from the second amplifier stage. Even further, the circuit includes an output port for emitting an output signal that is a rectified combination of the first input signal and the second input signal. Also, a method of processing signals input into a signal strength indicator circuit.

Abstract: A wireless access point includes, in one embodiment, circuitry with a radio transceiver that determines substantially optimal antenna orientation for one or more radio hosts with which an access point is in communication. Received RF signals are down-converted to baseband frequencies and produced to a baseband processor. At least one received signal strength indicator provides signal strength measurements for received communication channels to the baseband processor in the described embodiment. The baseband processor produces control signals to prompt the user to orient at least one antenna into a specified location. In one embodiment, logic prompts the user to move the antenna into a plurality of positions and then evaluates signal strength indication in each position to determine an overall substantially optimal orientation for all of the radio transceivers in communication with the access point.

Abstract: A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller (“DAC”), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially. The invention can be implemented as a Z/kZ ladder network, where k is a real number.

Abstract: A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory are off-chip.

Abstract: A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port.

Abstract: Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function call causes the cryptography accelerator to execute multiple cryptographic operations in a manner tailored for specific processing steps, such as steps during a handshake phase of a secured session. The techniques provide efficient use of hardware processing resources, data interfaces, and memory interfaces.

Abstract: An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure.

Abstract: A plurality of groups of first flip-flops (group 40 of flip-flops A1–An?1 for each of channels CIA–CIC) store input data clocked in response to first clock signals (A–C). First enable signals (Stack_en) are generated for each group of first flip-flops. A plurality of groups of second flip-flops (group 60 of flip-flops B1–Bn for each of channels CIA–CIC) store the input data from the first flip-flops in response to the first enable signals and first clock signals. A second enable signal (Slide_en) is generated in response to a second clock signal (D) and the first enable signal. A plurality of groups of third flip-flops (group 80 for each of channels CIA–CIC) store the data in response to the second enable signal and second clock signal. The data is transmitted in serial form at the rate of the second clock signal.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. An IC die is mounted to the first substrate surface. A plurality of solder balls is attached to the second substrate surface. A thermal connector is mounted to the second substrate surface. The thermal connector is configured be coupled to a printed circuit board.

Abstract: An improved cell layout for a C3MOS circuit with inductive broadbanding positions the inductor at a distance from the active region to improve isolation and aligns the edges of the resistor, inductor, and transistor regions near the common edge of adjacent cells to decrease the length of the cell-to-cell interconnect lines.

Abstract: A communication system includes an integrated circuit (IC) die having an on-chip source termination. The on-chip source termination can be a non-precision resistor, such as an unsilicided poly resistor, or any other suitable termination. As compared to an off-chip source termination, the on-chip source termination can reduce voltage peaking and/or voltage overshoot in the IC die and/or at a load that is connected to the IC die. The IC die can further include a line driver to provide a source current. A bias generator can be included to provide a bias current to the line driver. The bias generator can include a first current source coupled to an off-chip resistor and a second current source coupled to an on-chip resistor. An output voltage of the IC die can be adjusted by manipulating a trim control of the off-chip resistor and/or a trim control of the on-chip resistor.

Abstract: A continuous time filter having a first stage and a second stage. A first stage adjusts a bandwidth of the signal. A second stage adjusts bandwidth of the signal subsequent to the first stage. Each stage includes a first capacitor with a first capacitance and a second capacitor with a second capacitance for providing uniform step sizes for bandwidth adjustment. The continuous time filter may include a plurality of cascaded stages including the first stage and the second stage. In addition, a bandwidth adjustment across the first stage and the second stage may be controlled using a semi-interleaved thermometer coding to achieve a cascaded effect for the bandwidth adjustment.

Abstract: The programmable slew rate driver uses separate and programmably selectable resistors for time constants for on and off transitions on the NMOS and PMOS output transistors. By proper setting of gate voltage time constants and overlap of NMOS and PMOS “on” times, a desired output slew rate is accomplished, having a smooth output transition, without generation of shoot-through current. The programmable slew rate driver includes a first driver transistor coupled between the first supply voltage and output, a second driver transistor coupled between the second supply voltage and output, a plurality of upper transition blocks coupled in parallel and a plurality of lower transition blocks coupled in parallel between the first and second supply voltage. The rates of change and overlap of the gate voltages are in turn substantially determined by the resistance of the lower transition control blocks and the capacitance of the gate of the second driver transistor.

Abstract: A threshold adjustment circuit including: a current DAC for supplying or sinking a varying current; a differential pair of thin oxide transistors coupled to the DAC and coupled together at a common source node; a power supply for providing a supply voltage having a voltage level above reliability of the thin oxide transistors; and a third transistor for maintaining voltage of the common source node above a predetermined level and to disable the threshold adjustment circuit. The bulk and source of each of the differential pair thin oxide transistors is coupled to the common source node and each of the differential pair thin oxide transistors is switched by a signal to keep each of the differential pair thin oxide transistors in saturation region.

Abstract: A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting a gain of the signal. At least one differential pair in each stage is permanently enabled. The variable gain amplifier may include a plurality of cascaded stages including the stage. In addition, the variable gain amplifier may be adjusted through an interleaved thermometer coding method.