Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.
Type:
Application
Filed:
August 1, 2006
Publication date:
November 30, 2006
Applicant:
Broadcom Corporation
Inventors:
Siavash Fallahi, Chun Chen, Mark Chambers
Abstract: A charge pump includes a resistor divider connected between an output voltage node and ground and a comparator inputting a reference voltage at one input, and a divided voltage from the resistor divider at another input. A digital control circuit is enabled by the comparator. A first transistor and a second transistor are in series between an input voltage node and the ground, both transistors controlled by the digital control circuit. A pump capacitor is connected between to the output voltage node and between the first and second transistor, and being charged by turning the first and second transistors on and off. A first diode is between the pump capacitor and the input voltage node. A second diode between the pump capacitor and the output voltage node. A reservoir capacitor between the output voltage node and ground. The digital control circuit comprises a first shift register.
Abstract: A transport protocol receiver for receiving a packet from a network, the packet having a header, payload, and connection context. The receiver includes an analysis engine, coupled to receive the packet from the network and adapted to parse and validate the header, locate the connection context, and generate a classification of the header. The receiver further includes a context processing engine, coupled to the analysis engine, and adapted to evaluate and update the connection context, responsive to the classification; and a data dispatch engine, coupled to the analysis engine and the context processing engine, and adapted to convey the payload to a destination, responsive to the connection context, such that the analysis engine, the context processing engine, and the data dispatch engine operate substantially asynchronously.
Abstract: A digital-to-analog converter (DAC) disposed in a data transmission path to convert data from a digital format to an analog format to be transmitted is powered down during a receive mode of operation for a wireless communication device. Likewise, an analog-to-digital converter (ADC) disposed in a data reception path to convert received data from an analog format to a digital format is powered down during a transmit mode of operation.
Type:
Grant
Filed:
September 6, 2005
Date of Patent:
November 28, 2006
Assignee:
Broadcom Corporation
Inventors:
Gregory H. Efland, Venkat Kodavati, Gouri Pidugu, Srinivasa H. Garlapati
Abstract: Methods and apparatus are provided for implementing a cryptography engine for cryptography processing. A variety of techniques are described. A cryptography engine such as a DES engine can be decoupled from surrounding logic by using asynchronous buffers. Bit-sliced design can be implemented by moving expansion and permutation logic out of the timing critical data path. An XOR function can be decomposed into functions that can be implemented more efficiently. A two-level multiplexer can be used to preserve a clock cycle during cryptography processing. Key scheduling can be pipelined to allow efficient round key generation.
Abstract: A receiver includes a filter for filtering a received signal to produce a filtered signal. A converter converts the filtered signal to a baseband signal that is substantially free of an initial frequency offset and inter-symbol interference (ISI), responsive to a frequency-offset estimate and a restorative signal that compensates for the ISI. A detector detects symbols in the baseband signal to produce a decision signal. A restorative signal generator generates, from the decision signal, the restorative signal responsive to the frequency-offset estimate, such that the restorative signal compensates for the ISI.
Type:
Grant
Filed:
December 1, 2003
Date of Patent:
November 28, 2006
Assignee:
Broadcom Corporation
Inventors:
Thomas D Kwon, Jonathan S Min, Fang Lu, Thomas J Kolze
Abstract: An apparatus and method for enabling functionality of a component, wherein the apparatus includes a random number generating module for generating a random number, and a hash function module in communication with the random number generating module. A host is provided in communication with the random number generating module, and at least one memory in communication with the host is included. An encryption module in communication with the at least one memory is provided, and a comparing device in communication with the encryption module and the hash function module is included. The comparing device of the apparatus compares a first bit string to a second bit string to generate a function enable output for the component.
Abstract: A network interface is presented that receives packet data from a shared medium and accomplishes the signal processing required to convert the data packet to host computer formatted data separately from receiving the data packet. The network interface receives the data packet, converts the analog signal to a digitized signal, and stores the resulting sample packet in a storage queue. An off-line processor, which may be the host computer itself, performs the signal processing required to interpret the sample packet. In transmission, the off-line process converts host-formatted data to a digitized version of a transmission data packet and stores that in a transmission queue. A transmitter converts the transmission data packet format and transmits the data to the shared medium.
Type:
Grant
Filed:
May 9, 2000
Date of Patent:
November 28, 2006
Assignee:
Broadcom Corporation
Inventors:
Eric Ojard, Jason Trachewsky, John T. Halloway, Edward H. Frank, Kevin H. Peterson
Abstract: An operational amplifier includes a first stage with a first differential transistor pair inputting a differential input signal at their gates, a first tail current source transistor connected to sources of the first differential transistor pair, and a load transistor pair connected in series with the drain of first differential transistor pair. An input stage includes a second differential transistor pair connected to respective drains of the first differential transistor pair at their gates, and a second tail current transistor connected to sources of the differential transistor pair. An output stage outputs a signal corresponding to the differential input signal.
Abstract: A method and system are provided for removing discontinuities associated with synthesizing a corrupted frame output from a decoder including one or more predictive filters. The corrupted frame is representative of one segment of a decoded signal. The method comprises copying a first number of stored samples of the decoded signal in accordance with a time lag and a scaling factor, and calculating a first number of ringing samples output from at least one of the filters.
Abstract: A system for detecting connector compatibility with a time domain reflectometry (TDR) circuit on a peripheral device. A cable connects the peripheral device and a second peripheral device. A first connector is for mating to a second connector on the second peripheral device. The time domain reflectometry can be used to detect electrical compatibility of the first and second connectors. The first connector can be an RJ11 connector. The second connector can be an RJ45 connector. The first connector can be a plug, and the second connector can be a socket. The number of pins of the first and second connectors can be different. The first connector can be a telco connector, and the second connector can be an Ethernet connector. The TDR circuit can be part of the peripheral device diagnostics.
Type:
Grant
Filed:
August 2, 2004
Date of Patent:
November 28, 2006
Assignee:
Broadcom Corporation
Inventors:
James M. Muth, Peiqing Wang, Manolito M. Catalasan
Abstract: A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.
Type:
Grant
Filed:
July 18, 2005
Date of Patent:
November 28, 2006
Assignee:
Broadcom Corporation
Inventors:
Josephus A. E. P. Van Engelen, Kwang Young Kim, Mark Jonathan Chambers
Abstract: A packet-based, hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting substantially different characteristics are employed in an overall scheme to link portable or mobile computing devices. The network accommodates real time voice transmission both through dedicated, scheduled bandwidth and through a packet-based routing within the confines and constraints of a data network. Conversion and call processing circuitry is also disclosed which enables access devices and personal computers to adapt voice information between analog voice stream and digital voice packet formats as proves necessary. Routing pathways include wireless spanning tree networks, wide area networks, telephone switching networks, internet, etc., in a manner virtually transparent to the user.
Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.
Abstract: A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.
Abstract: The invention relates to generating a test suite of instructions for testing the operation of a processor. A fuzzy finite state machine with a plurality of states 2 and transitions 4 determined by weights W1, W2 . . . W10 is used to generate a sequence of instructions. The weights determine the next state as well as an instruction and operands for each state. The weights may be adapted based on the generated sequence and further sequences are generated.
Abstract: A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred embodiment, the contents of a base register is combined respectively with each of two or more packed objects in an offset register.
Abstract: A technique for performing frame erasure concealment (FEC) in a speech decoder. One or more non-erased frames of a speech signal are decoded in a block-independent manner. When an erased frame is detected, a short-term predictive filter and a long-term predictive filter are derived based on previously-decoded portions of the speech signal. A periodic waveform component is generated using the short-term predictive filter and the long-term predictive filter. A random waveform component is generated using the short-term predictive filter. A replacement frame is generated for the erased frame. The replacement frame may be generated based on the periodic waveform component, the random waveform component, or a mixture of both.
Abstract: A method and system to determine when a wireless terminal has been paged by a servicing base station. An encoded paging burst is received on a paging channel and then decoded to produce a decoded paging burst. The decoded paging burst is processed to determine if it is a null page. When the encoded paging burst is a null page, it is processed to produce a null page pattern. The wireless terminal may then enter a sleep mode or reduced functionality mode for a predetermined period of time. The wireless terminal awakes from the sleep mode to receive additional encoded paging bursts. Processing the additional encoded paging bursts produces a processed encoded paging burst, which is compared to the null page pattern. When compared favorably, the encoded paging burst is considered a null page, allowing the wireless terminal to re-enter the sleep mode without fully decoding the paging burst.
Type:
Application
Filed:
July 27, 2006
Publication date:
November 23, 2006
Applicant:
Broadcom Corporation, a California Corporation
Abstract: RF communications received by a wireless terminal from a servicing base station are used to determine the downlink quality report and implement link adaptation decisions. This involves first implementing an initial transmission scheme between the servicing base station and the wireless terminal. Next, a current downlink quality report corresponding to the initial transmission scheme is generated by the wireless terminal and received at the servicing base station. This downlink quality report is based in whole or in part on a bit-error probability (BEP). The current downlink quality report that corresponds to the initial transmission scheme is then compared to link adaptation thresholds.
Type:
Application
Filed:
July 27, 2006
Publication date:
November 23, 2006
Applicant:
Broadcom Corporation, a California Corporation