Abstract: A magnetic interface generator generates a magnetic interface at a center frequency f0. The magnetic interface generator is a passive array of spirals that are deposited on a substrate surface. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length DAV of the spirals in the spiral array. In embodiments, the spiral array is one sub-layer in a multi-layer substrate. The spacing S of the spiral array is chosen to project the magnetic interface to another layer in the multi-layer substrate so as to improve performance of a circuit in the plane of the magnetic interface.

Abstract: Systems and methods of printer resource sharing in a communication network are provided. In one embodiment, the system may comprise, for example, at least one communication device, a communication network, print server software, and at least one personal printer resource. The communication device may be deployed at a location. The communication network may be communicatively coupled to that communication device. The print server software may receive from the communication device via the communication network a request for printing of information content. The print server software may respond by coordinating the printing of the information content. The at least one personal printer resource may be communicatively coupled to the at least one communication device. The print server software may reside outside of the at least one personal printer resource, and the at least one personal printer resource may be accessed for printing by the communication device via the communication network.

Abstract: A relatively straight-forward implemented, and computationally efficient approach of selecting a predetermined number of unused codes is used to perform weighted linear combination selectively with each of the input spread signals in a multiple access communication system. If desired, the predetermined number of unused codes is always the same in each implementation. Alternatively, the predetermined number of unused codes are selected from within a reordered code matrix using knowledge that is shared between the two ends of a communication system, such as between the CMs and a CMTS. While the context of an S-CDMA communication system having CMs and a CMTS is used, the solution is generally applicable to any communication system that seeks to cancel narrowband interference. Several embodiments are also described that show the generic applicability of the solution across a wide variety of systems.

Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller.

Abstract: Methods of optimizing a plurality of numerically controlled delay lines (NCDLS) in a DDR memory controller are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: acquiring a plurality of statistics, the plurality of statistics defining an operating region for the DDR memory controller; and calculating optimal values for the plurality of NCDLs, the optimal values calculated using the plurality of statistics.

Abstract: A compensation circuit compensates for the variation in the internal resistance of a multi-track inductor over temperature. The compensation circuit includes a dummy inductor that has the same temperature dependent resistance as that of the multi-track inductor that is to be compensated. A first field effect transistor is placed in series with the multi-track inductor that is to be compensated, and a second field effect transistor is placed in series with the dummy inductor, where the gates of the FETs are tied together. A control circuit provides a constant current for the dummy inductor and detects any changes in voltage of the dummy inductor over temperature. The control circuit includes a feedback loop that controls the gate voltage of both first and second FETs so as to compensate for the temperature dependent inductor resistance variations of both the dummy inductor and the multi-track inductor that is to be compensated.

Abstract: For a high frequency buffer, a high frequency output path may be isolated from a low frequency feedback path using a common mode feedback loop. The common mode feedback loop may be utilized to adjust an output DC level. The common mode feedback loop may comprise a first differential amplifier and a first transistor. An output of the first differential amplifier may be coupled to an input of the first transistor, and the low frequency feedback path may communicate the output DC level from an output of the first transistor to a first input of the first differential amplifier. A reference voltage may be communicated to a second input of the first differential amplifier, and this reference voltage may be variable. The first differential amplifier may be adapted to compare the inputs and generate a control voltage, which may be utilized to adjust the output DC level.

Abstract: Communication decoder employing single trellis to support multiple code rates and/or multiple modulations. A single trellis is employed by the decoder to decode a plurality of encoded symbols. Each of the plurality of encoded symbols is governed by a rate control. A rate control sequence, having a period, is used to decode the plurality of encoded symbols that may be arranged within a frame. Various parameters of the plurality of encoded symbols may vary on a symbol by symbol basis; these parameters may include modulation, constellation, mapping, and/or bandwidth efficiency. For example, various symbols may be encoded differently, yet they may all be decoded using the same trellis. The functionality of this decoder may be implemented within a variety of different decoder embodiments including a trellis code modulation (TCM) decoder, a turbo trellis code modulation (TTCM) decoder, and/or a parallel concatenated turbo code modulation (PC-TCM) decoder.

Abstract: A method of performing an excitation Vector Quantization (VQ) in a Noise Feedback Coding environment involves reorganizing a calculation of an energy of an error vector for each of a plurality of candidate excitation vectors of a codebook. The energy of the error vector is a cost function that is minimized during a search of the codebook for a best candidate excitation VQ vector. The reorganization includes expanding a Mean Squared Error (MSE) term of the error vector, excluding an energy term that is invariant to the candidate excitation vector, and pre-computing energy terms of ZERO-STATE responses of the candidate excitation vectors that are invariant to sub-vectors of a subframe. Another method searches a signed codebook. Both methods use correlation techniques.

Abstract: A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; hierarchically-coupled local and global row decoders; and a predecoding circuit coupled with selected global row decoders. The predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory access speed of the memory structure, allowing access to a memory cell at least twice during the memory access period, thereby providing dual-port functionality. A WRITE-AFTER-READ operation without a separate, interposed PRECHARGE cycle, is completed within one memory access cycle of the hierarchical memory structure. The method includes locally selecting the first memory location of a first datum; locally sensing the first datum (i.e.

Abstract: One or more methods and systems of improving the performance of consecutive data stores into a cache memory are presented. In one embodiment, the method comprises writing data into a data array associated with at least a first store instruction while accessing a tag in a tag array associated with at least a second store instruction. In one embodiment, the method of processing consecutive data stores into a cache memory comprises updating a first data in a cache memory while concurrently looking up or identifying a second data in the cache memory. In one embodiment, a system for improving the execution of data store instructions of a CPU comprises a pipelined buffer using a minimal number of data entries, a data array used for updating data associated with a first store instruction, and a tag array used for looking up data associated with a second store instruction.

Abstract: A fast starting on-chip crystal oscillation circuit includes a power supply (Vdd) integrated circuit pad, a power return (Vss) integrated circuit pad, a 1st crystal integrated circuit pad, a 2nd crystal integrated circuit pad, a 1st transistor, a 2nd transistor, an inverter, a resistor, and two capacitors. The 1st and 2nd crystal IC pads couple a 1st and 2nd node of an external crystal oscillator to the fast starting on-chip crystal oscillation circuit. The 1st transistor, when activated, couples a power source connection of the inverter to the Vdd IC pad. The 2nd transistor, when activated, couples a power return connection of the inverter to the Vss IC pad. The input of the inverter is coupled to the 1st crystal IC pad and the output of the inverter is coupled to the 2nd crystal IC pad. The resistor is coupled in parallel with the inverter while the 1st capacitor is coupled to the input of the inverter and to the Vss IC pad. The 2nd capacitor is coupled to the output of the inverter and to the Vss IC pad.

Abstract: A receiver portion of a radio includes an analog circuit for determining a peak amplitude in a way that eliminates or reduces the effects of frequency errors that are introduced by crystals within filters and other devices. A voltage follower and a current mirror in which a MOSFET coupled to an output node produces a voltage across its gate to source terminals whose value is a function of a sum of the gate to source voltages of two MOSFET devices that receive a logarithm of an I modulated channel and a logarithm of a Q modulated channel, respectively.

Abstract: A system for connecting multiple repeaters into a single collision domain comprising a first repeater, a second repeater and a stacking bus. The first repeater has a plurality of network ports. The second repeater also has a plurality of network ports. The stacking bus connects the first repeater and the second repeater and is configured to relay status signals between the first and said second repeaters.

Abstract: A self-calibrating transmitter includes an up-conversion mixing module, summing module, calibration determination module, and a calibration execution module. The up-conversion mixing module is operably coupled to mix an I component of a base-band signal with an I component of a local oscillation to produce a mixed I signal and is also operably coupled to mix a Q component of the base-band signal with a Q component of the local oscillation to produce a mixed Q signal. The summing module sums the mixed I signal with the mixed Q signal to produce a modulated radio frequency (RF) signal. The calibration determination module is operably coupled to produce a calibration signal, which it generates by interpreting the local oscillation and the modulated RF signal. The calibration execution module is operably coupled to calibrate the DC level of the I and/or Q component of the base-band signal, and/or the gain of the I and/or Q component of the base-band signal based on the calibration signal.

Abstract: A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.

Abstract: A low noise amplifier includes an input transistor, an inductor, and a current sink. The input transistor includes a gate, a drain, and a source, wherein the gate of the input transistor is operably coupled to receive an input radio frequency (RF) signal. The inductor includes a first node and a second node, wherein the first node of the inductor is operably coupled to a power supply and the second node of the inductor is operably coupled to the drain of the input transistor to provide an output of the low noise amplifier. The current sink includes a first node and a second node, wherein the first node of the current sink is operably coupled to the source of the input transistor and the second node of the current sink is operably coupled to a circuit ground, wherein a real component of input impedance of the low noise amplifier is substantially constant when the low noise amplifier is in the off mode as when the low noise amplifier is in the on mode.

Abstract: A power amplifier includes an input transistor, an output transistor, and circuitry. The input transistor includes an input, a first node, and a second node, wherein the second node of the input transistor is coupled to a supply voltage return and the input of the input transistor operably coupled to receive an outbound radio frequency (RF) signal. The output transistor includes an input, a first node, and a second node, wherein the first node of the output transistor is coupled to provide an output of the power amplifier, the second node of the output transistor is coupled to the first node of the input transistor.

Abstract: A method to expand a RAID subsystem from a first array of disk drives to a second array of disk drives. The first array includes a set of data disk drives storing old data and spare space, and the second array includes the first array and at least one new disk drive. First, the old data are distributed among the set of data disk drives and at least one new disk drive while, at the same time, new data are mapped to the spare space. Upon completion of the distribution, the new data are copied from the spare space to the set of data disk drives and at least one new disk drive to enable concurrent expansion of the first array while accessing the old and the new data.

Abstract: A method and system for creating an ethernet-formatted packet from an upstream DOCSIS packet. The upstream packet is first received along with packet characteristic data that is contained in physical layer prepend data and in the packet header. A packet tag is then created, based on the packet characteristic data. The packet characteristic data includes identifiers for the transmitting remote device and the channel over which the transmission is sent. Packet characteristic data also includes information about the physical characteristics of the transmission signal, such as the power level and time offset. The packet characteristic data also includes administrative information, such as the minislot count at which the packet is received and whether the packet was received in contention. The packet tag is appended to the payload of the upstream packet. Also appended to the payload is an encapsulation tag, and source and destination address headers. The result is a packet in an ethernet format.