Abstract: A shielding apparatus was developed to eliminate electromagnetic waves interference (EMI) to an integrated circuit (IC) die while it is under test. The shielding apparatus comprises a conductive plate having a first and second surfaces and a central opening where the IC device is placed. The first surface includes a first EMI gasketted channel and a central cavity disposed inside of the gasketted channel. The second surface of the apparatus includes a second EMI gasketted channel and the central opening which extends through both the first and second surfaces. When the first surface mates with the surface of automatic test equipments (ATE) interface board, the first gasketted channel forms a tight seal. Similarly, when a plunger from a device handler mates with the second surface, the second EMI gasketted channel forms a seal that blocks out EMI. In this way, the IC device in the central opening of the apparatus is isolated from external EMI.

Abstract: A phase synchronizer may operate, for example, to establish synchronization with a phase of a received codeword. The phase synchronizer may include, for example, an input shift register, a first syndrome computing module, a first error detection module, a second syndrome computing module, a second error detection module and a comparator arrangement. The first syndrome computing module may compute syndromes relating to a first potential phase of the codeword. The first error detection module may determine, based upon the first syndromes, a first number of errors associated with the first potential phase of the codeword. The second syndrome computing module may compute syndromes relating to a second potential phase of the codeword. The second error detection module may determine, based upon the second syndromes, a second number of errors associated with the second potential phase of the codeword.

Abstract: A high gain, highly linear mixer includes an input section, mixing section, at least one tuning component, and at least one stand by current source. The input section is operably coupled to receive an input voltage signal and perform a linear transconductance thereon to produce an input current signal. The mixing section is operably coupled to mix a local oscillation with the input current to produce a mixed current signal. The tuning component is operably coupled to the mixing section and to convert the mixed current signal into a mixed voltage signal that function as the output of the mixer. The standby current source is operably coupled to the mixing section and provides a standby current to the mixing section.

Abstract: A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.

Abstract: RF communications received by a wireless terminal from a servicing base station are used to determine the downlink quality report and implement link adaptation decisions. This involves first implementing an initial transmission scheme between the servicing base station and the wireless terminal. Next, a current downlink quality report corresponding to the initial transmission scheme is generated by the wireless terminal and received at the servicing base station. This downlink quality report is based in whole or in part on a bit-error probability (BEP). The current downlink quality report that corresponds to the initial transmission scheme is then compared to link adaptation thresholds.

Abstract: An apparatus for providing a programmable gain attenuator (PGA) while minimizing the influence of semiconductor switches on the signal being attenuated. An example apparatus comprises a impedance ladder with taps forming the junctions between impedances the PGA is then programmed by grounding the taps through terminating resistors.

Abstract: A single chip radio transceiver includes circuitry that enables detection of radar signals to enable the radio transceiver to halt communications in overlapping communication bands to avoid interference with the radar transmitting the radar pulses. The radio transceiver is operable to evaluate a number of most and second most common pulse interval values to determine whether a traditional radar signal is present. The radio transceiver also is operable to FM demodulate and incoming signal to determine whether a non-traditional radar signal such as a bin-5 radar signal is present. After FM demodulation, the signal is averaged wherein a substantially large value is produced for non-traditional radar signals and a value approximately equal to zero is produced for a communication signal that is not FM modulated with a continuously increasing frequency signal. Gain control is used to limit incoming signal magnitude to a specified range of magnitudes.

Abstract: The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

Abstract: A design of integrated circuit components to prevent accidental turn on when large input signals are accepted. With integrated circuits operated at lower power supply voltages, input signals having large peak values can tend to turn on devices within the integrated circuit erroneously. By placing amplifiers within the integrated circuits where input signals are received and removing the power of such amplifiers, accidental turn on can be minimized.

Abstract: The present invention provides a frequency-diverse single-carrier modulation scheme that extends the usable SNR range of severely distorted channels. This scheme is advantageous for applications in which when the SNR is low and the transmitted spectrum contains unusable regions (e.g., spectral nulls due to radio-frequency interference ingress or egress). In one embodiment, the symbol baud rate is selected in order that unusable portions of the frequency response of the transmission channel are mapped onto usable portions of the frequency response of the transmission channel.

Abstract: A multi-modulus divider for producing a low-noise divided output, wherein one embodiment comprises a low-noise frequency divider comprising a pulse-swallow configured divider module and first, second, and third latching blocks. The pulse-swallow configured divider module produces a pre-scaled divider output and a divided oscillation. The divided oscillation is sequentially latched by the latching blocks, wherein the divided oscillation and pre-scaled divider output, coupled as clocks to the latching blocks, resynchronize the divided oscillation to substantially eliminate noise. The first and second latching blocks are biased by a first bias signal and the third latching block is biased by a second bias signal wherein the second bias signal is larger than the first bias signal. Each latching block includes an output load device wherein the impedance of the third latching block is smaller than the impedance of the other output load devices.

Abstract: A reference ladder is configured to have improved feedback stability. The reference ladder includes a resistor ladder having a plurality of taps that produce a plurality of reference voltages. The resistor ladder is driven by a first current source at a first tap of the plurality of taps and by a second current source at a second tap of the plurality of taps. A first feedback network senses a voltage at the first tap and controls the first current source based on the first sensed voltage. A second feedback network senses a voltage at the second tap and controls the second current source based on the second sensed voltage. The first and second taps each operate as both a force tap and a sense tap of the resistor ladder. Differential input stages that are connected to the plurality of taps are at least partially isolated from the feedback networks by converging the force and sense taps, thereby improving the stability of the feedback networks.

Abstract: A single side band transmitter having reduced DC offset includes a current source modulation module, a current mirror module, a 1st mixing module, a 2nd mixing module, a summing module, and a power amplifier. The current source module is operably coupled to modulate, in accordance with a modulation protocol (e.g., FSK) data to produce an in-phase current component and a quadrature current component. The current mirror module is operably coupled to mirror the in-phase current component to produce a mirrored in-phase current component and is also operably coupled to mirror the quadrature current component to produce a mirrored quadrature current component. The 1st mixing module is operably coupled to mix the mirrored in-phase current component with an in-phase current component of a local oscillation to produce a 1st mixed current signal.

Abstract: A network switch for network communications, wherein the network switch includes at least one data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate and a second data rate. The at least one data port interface includes an ingress logic circuit in communication with the at least one data port interface for generating at least one of an ingress address resolution and a filtering search request. A CPU interface is provided and configured to communicate with a CPU. A shared hierarchical memory structure including an internal memory in communication with the at least one data port interface, and an external memory in communication with a memory management unit via an external memory interface is provided. A communication channel is provided for communicating data between the at least one data port interface, the internal memory, the CPU interface, and the memory management unit.

Abstract: Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.

Abstract: A system and method for efficiently detecting and decoding valid teletext message sequences is provided. A system is provided that includes a correlator, a sine wave generator, two time window generators, a phase detector, a framing code search engine, and a match filter. The method includes determining the phase of the run-in burst of a teletext message sequence, identifying the framing code location, deciding whether the teletext sequence is valid, and decoding the teletext data for display.

Abstract: A transceiver includes a transmitter portion with an analog modulator that modulates data using frequency shift keyed (FSK) modulation techniques to increase efficiency, reduce power consumption, and reduce IC real estate in comparison to current digital FSK modulation circuits. The analog modulator comprises a loop that includes a pair of integrators and a pair of mixers. In at least one embodiment, the pair of mixers comprises switches that control a polarity of a modulated output signal that is produced to an up-conversion module for up-conversion to RF. The up-conversion module, then, when mixing the modulated output signal with a local oscillation signal, produces an output having one of two possible frequencies wherein the frequencies are a function of the polarity of the modulated output signal.

Abstract: A system and method for interference reduction in a spread spectrum receiver including a rake receiver having a plurality of fingers for processing a plurality of data signals and an associated plurality of pilot signals is disclosed herein. The method includes generating a plurality of intra-finger interference cancellation signals using the plurality of pilot signals. In this regard each of the plurality of intra-finger interference cancellation signals are associated with one of the plurality of fingers. Ones of the plurality of intra-finger interference cancellation signals are weighted so as to generate a set of weighted intra-finger interference cancellation signals. The method further includes synthesizing at least one inter-finger interference cancellation signal in accordance with the set of weighted intra-finger cancellation signals. At least one inter-finger interference cancellation signal may then be subtracted from a corresponding one of the plurality of data signals.

Abstract: A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a headend and a plurality of cable modems located different distances from the headend. The power transmission level, slot timing, and equalization of the cable modems are set by a ranging process. Data is transmitted by the modems in fragmented form. Various measures are taken to make transmission from the cable modems robust. The upstream data transmission is controlled to permit multiple access from the cable modems.

Abstract: Certain embodiments for ensuring the assertion order of signals in a chip independent of physical layout may comprise receiving a first signal by a first logic block of a plurality of logic blocks integrated within a chip, where the first signal may initiate a reset of a first function within the first logic block. A second signal may be communicated from within the first logic block to a second function within a second logic block of the plurality of logic blocks, and the second signal may be adapted to initiate the second function. The first signal may be the same as a second signal. The reset of the first function may initialize the first function to a known state before the second function may generate an output that may be received by the first function. The first function may place the chip in a test mode when indicated by the generated output of the second function.