Abstract: A method for decoding a received word, including calculating a syndrome of the received word as a plurality of binary element vectors, generating respective logarithms of the binary element vectors, and determining, in response to the logarithms, an indication of a position of an erroneous bit in the received word.

Abstract: An integrated circuit includes at least a first fuse and at least a first processor. Each fuse is in either a conductive state or a non-conductive state. The first processor is configured to operate at one of at least a first issue rate or a second issue rate responsive to the state of the first fuse. The first issue rate is lower than the second issue rate. In another embodiment, the first processor is configured to execute fewer instructions in a period of time responsive to a first state of the conductive state or the non-conductive state of the first fuse than the first processor is configured to execute in the period of time responsive to a second state of the first fuse. A method includes: (i) determining if an integrated circuit comprising at least one processor has a performance rating that exceeds a government-imposed export restriction; and (ii) in response to the performance rating exceeding the export restriction, blowing at least one fuse on the integrated circuit.

Abstract: A content addressable memory cell (10) includes a circuit (20) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first point (35) and a second bit of complementary data at a second point (36). A first transistor (40) comprising a first gate (42) is switchable to first and second states in response to predetermined relationships between the first and second bits and third and fourth test bits transmitted on first and second lines (14 and 16). Second and third transistors (50, 60) comprise gates (52, 62) coupled to the first line (14) and second line (16) and comprise circuit paths (54, 56, 64, 66) coupling the first and second points to the first gate.

Abstract: A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing.

Abstract: An RFIC includes a baseband processing module, a digital to analog converter, an analog to digital converter, a radio module, and a border section. The border section is fabricated on the substrate, wherein the border section physically separates the radio module from the baseband processing module, the digital to analog converter, and the analog to digital converter, wherein the border section includes noise suppression circuitry operably coupled to convert outbound baseband signals into low noise outbound baseband signals and to convert low noise inbound baseband signals into inbound baseband signals.

Abstract: A direct conversion tuner down-converts television signals, cable signals, or other signals directly from an RF frequency to an IF frequency and/or baseband, without an intermediate up-conversion step for image rejection. The direct conversion tuner includes a pre-select filter, an amplifier, an image reject mixer, and a poly-phase filter. The pre-select filter, amplifier, and the image reject mixer can be calibrated to provide sufficient image rejection to meet the NTSC requirements for TV signals. The entire direct conversion tuner can be fabricated on a single semiconductor substrate without requiring any off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: An internet protocol telephone includes a substrate having an input and an output that are capable of being connected to the internet protocol (IP) network. A relay is disposed on the substrate and is connected between the input and the output of the substrate. The relay includes first and second native FETs that have a threshold voltage of approximately zero volts. Therefore, the relay is nominally turned-on, even when little or no voltage (or power) is applied to the IP telephone substrate, as during the discovery mode of IP telephone operation. During discovery mode, The IP phone is configured to be responsive to extended link pulses and block data packets that are associated with legacy devices. Data packets have a higher signal duration and are more continuous than extended link pulses. The IP phone includes a switchable ground that is connected to the gates of the native devices, and is controlled by a rectifier and filter circuit that are connected to the substrate input.

Abstract: A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.

Abstract: The present invention provides an apparatus and method for providing a programmable inverse discrete cosine transform, wherein the transform coefficients are loaded into a memory area of a core transform device and a variety of coding standards can thereby be handled by the same programmable core device. The core device is configured to process a certain sized data block, and the incoming source blocks are converted to conform to this size. After transformation, the proper sized result can be extracted from the transform device output. A switchable speed-up mode provides for 4-point transforms, rather than 8-point transforms. Alternatively, the invention also provides for dedicated transform hardware to be switchably used in conjunction with programmable transform hardware, depending upon the type of coding being used, and the speed of inverse transform desired.

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

Abstract: System and method for decoding variable-length codes. A variable-length decoder includes an address generator and a local memory unit. The local memory stores a variable-length code look-up table. The local memory can be programmed to include a look-up table supporting substantially any decoding algorithm. In one embodiment, a decoder memory unit and a system memory unit are employed together with the local memory to store a codeword look-up table. The shortest codes are stored in local memory, the next shortest in decoder memory, and the longest codes are stored in system memory. A multistage search algorithm is employed to search for the longest codes. The address generator generates the address of the code table to be searched by adding the value of the bits to be searched to a base address.

Abstract: A via provides a plurality of electrical connections between conductors on different layers of a circuit board. The via includes an opening through the circuit board formed by a plurality of substantially partially overlapping bores. An electrically conductive plating is formed on an inner surface of the opening. The plating forms a plurality of distinct electrically conductive paths.

Abstract: A peripheral bus switch includes a virtual peripheral bus, a plurality of bridges, and a configurable host bridge. A first bridge operably couples on a first side to the virtual peripheral bus and supports connection on a second side to a peripheral bus fabric. A second bridge operably couples on a first side to the virtual peripheral bus and supports connection on a second side to the peripheral bus fabric. The configurable host bridge operably couples to the virtual peripheral bus, supports a host mode of operation in which it serves as a host bridge, and supports a device mode of operation in which it operates as a device.

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software modes, is used with the plurality of memory cells to indicate that at least one memory cells is unusable and should be shifted out of operation. The software mode comprises a software programmable element adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware mode comprises a hardware element adapted to indicate the at least one memory cell is unusable and is gated with the software programmable element. The hardware and software modes act autonomously.

Abstract: A method of compressing a puncture mask information is disclosed, the method comprising making a delayed puncture mask by deleting the last k bits of the puncture mask; and appending k zeros to the beginning of the puncture mask; making a differential puncture mask by XORing the delayed puncture mask with the puncture mask; and compressing the differential puncture mask.

Abstract: A method for calibrating a phase locked loop (PLL) includes an open loop test and a closed loop test. The open loop test includes providing an optimal control input to a controlled oscillator (CO) of the PLL; determining rate of output oscillation of the CO based on the optimal control input; comparing the rate of the output oscillation with rate of an optimal output oscillation; and when the comparing the rate of the output oscillation with rate of the optimal output oscillation is unfavorable, adjusting an oscillation point of the CO until the comparing is favorable to produce an open-loop adjusted CO oscillation point.

Abstract: A voltage supply interface provides both coarse and fine current control with reduced series resistance. The voltage supply interface has a segmented switch having N component switches that are digitally controlled. The voltage supply interface replaces a conventional sense resistor with a calibration circuit that has a replica switch that is a replica of the N component switches. The calibration circuit includes a reference current IREF that is sourced through the replica switch. A voltage comparator forces a common voltage drop across the replica switch and the n-of-N activated component switches so that the cumulative current draw through the segmented switch is n·IREF. The current control of the voltage interface can be coarsely tuned by activating or deactivating component switches, and can be finely tuned by adjusting the reference current. The current sense resistor is eliminated so that the overall series resistance is lower.

Abstract: A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.

Abstract: In wireless communications such as in the Bluetooth communication system, an execution unit sequentially receives software instructions for execution. Prior to completing each instruction, the execution unit issues an interrupt indicating the upcoming completion of the instruction execution and awaits receipt of the next instruction. A Link Manager issues limited instructions, and a Link Controller includes a hardware execution unit for executing the limited instructions. A processing unit in the Link Manager performs remaining functions under control of a software program.

Abstract: A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer receives an output of the first flip flop and outputs peak data. A second demultiplexer receives an output of the second flip flop and outputs zero data. A timing recovery circuit outputs phase control bits based on the zero data and the peak data. A first phase interpolator outputs the 0° clock based on the phase control signal. A second phase interpolator outputs the 180° clock based on the phase control signal. A phase register receives the phase control signal from the timing recovery circuit. The first and second flip flops can be D flip flops. The first and second phase interpolators adjust relative phases of the 0° clock and 180° clock based on the phase control signal.