Abstract: In an integrated satellite receiver, improved header acquisition techniques are described for quickly locating a header symbol sequence in a data stream substantially implemented on a single CMOS integrated circuit. To identify the location of a header symbol sequence in a data stream, a selected header acquisition technique employs a real time correlator followed by an accumulator. In accordance with an alternative embodiment which reduces the cost very efficiently, a real time correlator is followed by a comparator to pick out and store the top N correlator values from NS symbols in a frame. The timing addresses associated with the stored correlator values are used during an accumulation mode of operation whereby a cumulative memory is used to accumulate the correlator value of each stored timing address. Once accumulation over a predetermined number of frames is finished, the largest or maximum value among the accumulated correlator values is identified.

Abstract: A method for controlling a flow of packet data in a memory management unit of a network switch fabric is disclosed. A first portion of a data packet is received at a port on an ingress bus ring of the network switch fabric. A class of service for the data packet is determined based on the first portion and the portion is stored in a packer RAM of the port based on the class of service. Subsequent portions of the data packet are stored in the packer RAM. Once the predetermined number of portions have been received, the predetermined number of portions is sent to a packet pool RAM. A reference pointer to a first predetermined number of portions is sent to a transaction queue once an end of packet is detected and an egress scheduler detects a presence of a ready packet in the transaction queue and notifies an unpacker of the ready packet. The unpacker puts the ready packet into a FIFO and the ready packet is sent to an ingress/egress module.

Abstract: A digital demodulator includes a mixing section, 1st and 2nd digital comb filters, phase locked loop module, and a data recovery module. The mixing section is operably coupled to produce a digital I signal and a digital Q signal from a digital intermediate frequency signal. The 1st comb filter filters the digital I signal while the 2nd comb filter filters the digital Q signal. The phase locked loop module produces a digital signal from the filtered I and filtered Q signals. The data recovery module interprets the digital signal to recapture a data stream.

Abstract: A system, method and computer program product is provided for mitigating the effects of burst noise on packets transmitted in a communications system. A transmitting device applies an outer code, which may include, for example, a block code, an exclusive OR (XOR) code, or a repetition code, to one or more packets prior to adaptation of the packets for transmission over the physical (PHY) layer of the communications system, wherein the PHY layer adaptation may include FEC encoding of individual packets. The outer coded packets are then separately transmitted over a channel of the communications system. A receiving device receives the outer coded packets, performs PHY level demodulation and optional FEC decoding of the packets, and then applies outer code decoding to the out6r coded packets in order to restore packets that were erased during transmission due to burst noise or other impairments on the channel.

Abstract: A buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for proficient division of the encoding task and quicker through put time. A single chip digital signal processing device for real time video/audio compression comprises a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

Abstract: A radio frequency integrated circuit includes a power amplifier, a low noise amplifier, a first transformer balun, and a second transformer balun. The power amplifier includes a first power amplifier section and a second power amplifier section. When enabled, the first and second power amplifier sections amplify an outbound radio frequency (RF) signal to produce a first amplified outbound RF signal and a second amplified outbound RF signal, respectively. The power amplifier provides the first amplified outbound RF signal to the first transformer balun and the second outbound RF signal to the second transformer balun, where the first transformer balun is coupled to a first antenna and the second transformer balun is coupled to a second antenna. The low noise amplifier includes a first low noise amplifier section and a second low noise amplifier section.

Abstract: An on-chip loop filter includes a 1st resistor, a 1st capacitor, a 2nd capacitor, a 3rd capacitor, a 2nd resistor, and a 4th capacitor. The 1st resistor is operably coupled to receive a charge pump output. The 1st capacitor is coupled in series with the 1st resistor where the second node of the 1st capacitor is coupled to a return. The 2nd capacitor is coupled in parallel with the series combination of the 1st resistor and 1st capacitor. The 3rd capacitor is coupled in parallel with the 2nd capacitor. The 2nd resistor is coupled to a node of the 3rd capacitor and to a node of the 4th capacitor. The other node of the 4th capacitor is coupled to ground.

Abstract: A differential mixer includes DC currents that reduce flicker noise in the mixer circuit without increasing local oscillator drive requirements. The differential mixer circuit includes an RF transconductance circuit and a local oscillator (LO) switching circuit. The RF transconductance circuit converts a differential RF input signal to a differential RF current. The LO switching circuit commutates the differential RF input signal according to a local oscillator signal to frequency translate the RF input signal. The DC currents or bleeder currents are added directly to the field effect transistors in the RF transconductance circuit, which reduces the flicker noise produced by the mixer. The DC currents do not pass through the FETs in the LO switching circuit so there is no increase in the LO drive requirements.

Abstract: An on-chip multiple tap transformer balun includes a 1st winding and a 2nd winding having two portions. The 1st winding is on a 1st layer of an integrated circuit and is operably coupled for a single ended signal. The 1st and 2nd portions of the 2nd winding are on a 2nd layer of the integrated circuit. The 1st portion of the 2nd winding includes a 1st node, a 2nd node, and a tap. The 1st node is operably coupled to receive a 1st leg of a 1st differential signal and the 2nd node is coupled to a reference potential. The tap of the 1st portion is operably coupled for a 1st leg of a 2nd differential signal. The 2nd portion of the 2nd winding includes a 1st node, 2nd node, and tap. The 1st node is operably coupled to receive a 2nd leg of the 1st differential signal and the 2nd node is operably coupled to the reference potential. The tap of the 2nd portion is coupled for a 2nd leg of the 2nd differential signal.

Abstract: A method and system are provided for accessing, monitoring, and controlling home appliances in a media exchange network by establishing a communication link between a communication initiation device and at least one home appliance and communicating at least one command from the communication initiation device to the at least one home appliance via the communication link. The at least one home appliance then generates at least one response to the at least one command. The commands may include turning the home appliance(s) on and off, parameter adjustment commands, access commands, monitoring commands, mode change commands, and programming commands. Appliance responses may include powering on, powering off, changing a mode of operation, sending a status to the communication initiation device, adjusting an operational parameter, and changing a programmed operational step.

Abstract: Circuits and a method to enhance scan testing by controlling clock pulses that are provided to flip-flops within an integrated circuit are provided. An integrated circuit is provided that includes a scan testing clock control circuit for flip-flops. The scan testing clock control circuit enables control of a clock input signal to one or more flip-flops within the integrated circuit. In one embodiment, a scan testing clock control circuit can be used to ensure that a flip-flop receives a clock input signal during scan testing. In one embodiment the scan testing clock control circuit includes a latch, and an AND gate. A method for scan testing using a scan testing clock control circuit for flip-flops is also provided.

Abstract: The present invention provides an apparatus and method to reduce the memory footprint of a processor architecture by structuring processor code to be stored in an external device, and transferring into the processor certain code and associated data as it is needed. The processor code or algorithm is divided into a controlling piece and a working piece. The controlling piece can be located on a low-MIPS, high memory-footprint device, whereas the working piece can be located on a high-MIPS, low memory-footprint device. The working piece can also be broken down into phases or segments, which are put in a data store. The segments are then transferred, on an as-needed basis along with associated data, from the store into the constrained memory of the low memory-footprint device. Transfer is facilitated by a segment manager which can be processed from the low-MIPS device, or alternatively from the high-MIPS device.

Abstract: A single ended highly linear power amplifier includes a component, a 1st transistor pair, and a 2nd transistor pair. The 1st and 2nd transistor pairs are coupled in series with the component, which may be a resistor, inductor and/or linearly loaded transistor, where the node coupling the component to the 1st and 2nd transistor pairs provides the output of the single-ended highly linear power amplifier. The 1st transistors of the 1st and 2nd transistor pairs are coupled to receive an input signal. The 2nd transistors of the 1st and 2nd transistor pairs are each coupled to receive a separate enable signal. The transistor pairs are enabled via their corresponding enable signal to change the gain of the power amplifier with negligible effects on the linearity of the power amplifier. A differential power amplifier includes the single ended power amplifier and a complimentary mirror image of the single ended power amplifier.

Abstract: The present invention is directed to a seal structure and a method for forming a seal structure for a semiconductor die. An elongate region which is electrically isolated from the remainder of the substrate, such as a well region of a conductivity type opposite that of the substrate, extends around the major portion of the periphery of the substrate. A gap is left between the two ends of the elongate region along the minor portion of the periphery of the substrate not covered by the elongate region. A conductive seal ring is formed around the periphery of the substrate at the elongate region and spans the gap between the ends of the elongate region. The substrate of the semiconductor die is only brought into electrical contact with the seal ring at the gap between the ends of the elongate region.

Abstract: A fast starting on-chip crystal oscillation circuit includes a (Vdd) IC pad, a (Vss) IC pad, a 1st crystal IC pad, a 2nd crystal IC pad, a 1st transistor, a 2nd transistor, an inverter, a resistor, and two capacitors. The 1st and 2nd crystal IC pads couple an external crystal oscillator to the fast starting on-chip crystal oscillation circuit. The 1st and 2nd transistors, when activated, couple power to the inverter. The input of the inverter is coupled to the 1st crystal IC pad and to the 1st capacitor. The output of the inverter is coupled to the 2nd crystal IC pad and to the 2nd capacitor. The resistor is coupled in parallel with the inverter. When the 1st and 2nd transistors are activated, an impulse voltage occurs between the 1st and 2nd crystal IC pads to initiate the oscillation of the crystal oscillator.

Abstract: A receiver comprises a first Variable Gain Amplifier (VGA) that amplifies an input signal in accordance with a first gain to produce a first amplified signal. The first gain is controlled based on the first amplified signal. The receiver includes a second VGA that produces a second amplified signal responsive to the first amplified signal. The second VGA has a second gain controlled based on the second amplified signal.

Abstract: Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.

Abstract: A printed bandpass filter is mounted on a precision substrate to eliminate the need for post-fabrication tuning. The filter input is capacitively coupled to a series of quarter wavelength resonators and the filter output. The quarter wavelength resonators are printed as spirals to reduce filter size. The resonators define the bandpass characteristics of the filter. The filter also weakly couples the input signal to the filter output in a manner to cancel the signal image. Mechanical clips mitigate thermal stress on solder connections when the precision substrate is mounted on a second printed circuit board.

Abstract: Close two constituent trellis of a turbo encoder within the interleave block. The state of a multi-state encoder is forced to a known/predetermined state at the end and beginning of each data frame. Packet based and/or frame based data transmissions benefit greatly when the encoder state of a multi-state encoder is known at the beginning and end of each frame. Appropriately chosen symbols, selected to force the encoder to a known state at the end of a data frame, may be padded to the end of a data frame that is to be encoded; this will force the encoder to “close” at the end of the data frame. These closure symbols may also be padded to the end of the data frame before the data frame in interleaved. Moreover, within encoder embodiments that include multiple constituent encoders, both constituent encoders will be forced to the known/predetermined state.

Abstract: A sequence mapping circuit and method for digital audio circuits generates a pulsed output. Over time, the mapping circuit generates pulses with a substantially identical average centroid for each of the possible output waveforms. For at least some of the output waveforms, two or more sets of pulses are provided representing the same waveform but having different centroids. The output is alternated among the available sets of pulses to maintain the desired average centroid over time. Shuffling of the output among the available pulses representing a given waveform may be randomly determined, or the pulses used may be tracked and the output pulses sequentially alternated among the available output pulses. The shuffled mapping method reduces output harmonics compared to conventional static mappers.