Abstract: A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of double-balanced IQ mixers. The double-balanced mixers include cross-coupled PMOS devices that dynamically inject current at zero-crossing points to cancel out tail currents in the mixers. Also, methods of operating the above-discussed receiver and receiver front end.

Abstract: An adaptive electronic transmission signal cancellation circuit for separating transmit data from receive data in a bidirectional communication system operating in full duplex mode is disclosed. The output of a main transmitter responsive to a first bias current is connected to the output of a receiver through an internal resistor. A first replica transmitter responsive to a second bias current and matched to the main transmitter current gain and rise/fall time characteristics is connected to the input terminal of the receiver, and produces a cancellation voltage between the output terminal of the main transmitter and the input terminal of the receiver as a function of the second bias current and the internal resistor.

Abstract: A system and method is provided for supplying power over a home phone line network in a manner that is interoperable with other voice and data services operating on the same network. The system includes a power source coupled to the home phone line network. The power source includes an AC signal generator that generates an AC signal at a selected frequency. The power source also includes a band pass filter for removing unwanted harmonics from the AC signal, thereby generating a filtered AC signal for powering one or more devices on the home phone line network. One or more devices attached to the home phone line network, such as a telephone adapter or telephone, receives the filtered AC signal. Each device comprises a second band pass filter and an AC/DC converter. The second band pass filter passes the filtered AC signal to the AC/DC converter and prevents the introduction of undesired harmonics onto the home phone line network from the AC/DC converter.

Abstract: A modem includes a Digital Access Arrangement (DAA) Circuit and modem software that is executed by a processor. When the DAA Circuit detects that the modem software is nonfunctional, it enters an on-hook state to prevent blocking of a coupled telephone line. A nonfunctional state of the modem software is detected when the modem software ceases to interact with the DAA Circuit in an expected manner. In a first operation, the nonfunctional state is determined when the modem software does not reset a count down timer in the DAA Circuit before the count down timer reaches a termination value. In a second operation, the nonfunctional state is determined when the modem software does not access the DAA Circuit before the count down timer reaches the termination value. In a third operation, the nonfunctional state is determined when the modem software ceases writing transmit data to DMA memory.

Abstract: A point-to-multipoint network interface is provided that is simpler and less costly to implement than conventional Ethernet switches. The interface includes a plurality of downstream transmitters for transmitting data packets to a plurality of end user devices, a plurality of downstream receivers for receiving data packets from the plurality of end user devices, an upstream transmitter and an upstream receiver. A multiplexer within the interface multiplexes data packets received from the end user devices into a stream of data packets for transmission to a higher level node regardless of the destination address of the data packets. Conversely, a demultiplexer within the interface demultiplexes a stream of data packets received from the higher level node into individual data packets for selective transmission to one of the plurality of end user devices. The interface can support asymmetrical transmission rates on the upstream and downstream channels between the interface and the end user devices.

Abstract: An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to provide a desired frequency of oscillation. More specifically, the oscillator includes a capacitor array that has a plurality of capacitors coupled in parallel wherein each capacitor may be selectively included into the RC time constant or selectively excluded there from. Rather than setting the capacitance values to a desired capacitance value, a system for adjusting the time constant includes circuitry for measuring an output frequency and for comparing that to a certified frequency source wherein the time constant is adjusted by adding or removing capacitors from the capacitor array until the frequency of the internal clock matches an expected frequency.

Abstract: Systems and methods that provide a one-time programmable (OTP) memory with fault tolerance are provided. In one example, the OTM memory may include a data portion and a multistage programming (MSP) portion. The data of the data portion may be protected by error coding. The MSP portion may include at least one MSP bit and at least one respective redundant MSP bit.

Abstract: A network switch and a method thereof for network communications include a first data port interface and a second data port interface supporting a data port transmitting and receiving data at a first data rate and a second data rate, respectively. The switch has a CPU interface to communicate with a CPU and a memory management unit to communicate data from at least one of the first and second data port interfaces and a memory. The switch includes a communication channel communicating data and messaging information between the first and second data port interfaces and the memory management unit and lookup tables, including an address resolution lookup table and a VLAN table. The first or second data port interfaces determine an egress port for an incoming data packet from a search of the address resolution lookup table and the VLAN table using a VLAN ID from the incoming data packet.

Abstract: A method and related computer program product for storing first configuration information for a plurality of logical devices coupled to a RAID controller. Subsequent configuration information is stored for the plurality of logical devices coupled to the RAID controller while retaining previously written configuration information. Finally, in the event of a conflict in configuration information, the first and subsequent configuration information is compared to determine the cause of the conflict.

Abstract: A method and apparatus for communicating within a system including a master unit and one or more slave units is disclosed herein. A member address, corresponding to a selected time slot of a plurality of time slots defined by a system clock configured to repeat in cycles, is assigned to a first slave unit. The first slave unit is also assigned a first extended address associated with an occurrence of the designated time slot within at least a selected one of the cycles. After being polled by the master unit during an immediately preceding time slot, the first slave unit transmits information thereto during the designated selected time slot within the selected cycle. A second slave unit may also be assigned the member address and a second extended address associated with a different occurrence of the selected time slot within one or more of the cycles. The second slave unit is disposed to transmit information during such different occurrence of the selected time slot.

Abstract: The present invention provides a method for prioritizing packet flows within a switching network. The method includes the steps of receiving packets at an input port, stamping the packets with an arrival time, and classifying the packet into a flow, wherein the flow is determined based upon at least a class of service of the packet, assigning the packet to a queuing ring according to the flow of the packet, and maintaining a flow ratio pending within the switch based upon the classification of the packet.

Abstract: An oscillating circuit having a noise reduction circuit is disclosed. The noise reduction circuit is coupled to the current source for the oscillating circuit. The noise reduction circuit reduces a bias noise component from a bias current, and a supply noise component from a supply current. The noise reduction circuit is coupled to the current source at a gate and a supply for the current source. The noise reduction circuit includes a filter coupled to the gate of the current source that reduces the bias noise component. The noise reduction circuit also includes a degeneration circuit coupled to the supply of the current source that reduces the supply noise component. The current source generates an input signal to control the oscillating circuit with reduced noise.

Abstract: A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.

Abstract: A system and method is used to tune filters, for example, analog filters in a sigma-delta modulator ADC. A known dither signal is used, for example a digital dither signal. Through adding of the dither to the modulator loop, the digital output of the sigma delta modulator ADC contains a filtered version of the digital dither. This signal can be used to reveal characteristics of the modulator-loop, including characteristics of a continuous-time filter in the modulator. Therefore, using the known digital dither signal and the output signal of the modulator, the continuous-time loop filter can be tuned. The tuning can be done in multiple ways, for example, by using standard LMS adaptive filter techniques to estimate the actual response of the continuous-time loopfilter and adjust the continuous-time loopfilter to the desired response.

Abstract: A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller (“DAC”), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially.

Abstract: A compensation apparatus maintains an effective resistance of one or more resistors in a circuit by associating an adjustable resistor circuit to each resistor. The compensation apparatus compares the resistance of a resistor in the circuit with the resistance of a reference resistor. When the resistance of the resistor in the circuit falls outside of a desired range, the compensation apparatus adjusts the resistance of the adjustable resistor to adjust the effective resistance of the resistor and adjustable resistor combination.

Abstract: Analog signals encoded with quadrature amplitude modulation (QAM) pass through a coaxial cable at a particular baud rate. These signals have a carrier frequency individual to the TV station being received. They are mixed with signals from a variable frequency oscillator to produce signals at a particular intermediate frequency (IF). An analog-digital converter (ADC) converts the IF signals to corresponding digital signals which are demodulated to produce two digital signals having a quadrature phase relationship. After being filtered and derotated, the digital signals pass to a symmetrical equalizer including a feed forward equalizer (FFE) and a decision feedback equalizer (DFE) connected to the FFE in a feedback relationship. The DFE may include a slicer providing amplitude approximations of increasing sensitivity at progressive times. Additional slicers in the equalizer combine the FFE and DFE outputs to provide the output data without any of the coaxial cable noise or distortions.

Abstract: Provided are a method and system for reducing glitch in a switch circuit. A system includes a current-steering switch circuit including a main differential pair switch coupled to a first tail current having a first current value. Also included is an auxiliary differential pair switch connected to the main differential pair switch. The auxiliary differential pair switch is coupled to a second tail current and configured to substantially reduce a feed-through current associated with the main differential pair switch.

Abstract: The invention refers to an apparatus and a method for reducing random noise in a sequence of digital video frames comprising the following steps: 1. for each of the pixels (center pixel) in a frame a set of adjacent pixels is defined; 2. for each of the adjacent pixels the difference of their values in the current frame and the previous frame is calculated, whereby the value of the center pixel is omitted; 3. each difference value is shifted right for a predefined number of bits; 4. the square of the difference value is added to an activity value of that center pixel; 5. if the activity value remains below a predefined threshold value, then a weighting factor depending from activity value is calculated and 6. the value of the center pixel is set to a weighted value.

Abstract: A multi-level power amplifier architecture using a multi-tap transformer implemented on a single CMOS integrated circuit wireless communications device is described. By providing a multi-tap transformer for coupling a plurality of power amplifiers to a shared output impedance, such as an antenna, power transmission may be made at different levels while maintaining efficiency. With a multi-tap transformer having “N” taps featuring “N” different impedance levels, each tap may be connected to an amplifier cell which delivers power into the transformer at the tap for coupling to the output load. Any one of the “N” amplifier cells can be turned on at once along with any combination of the “N” amplifier cells.