Abstract: A method and system for combing requests for data bandwidth by a data provider for transmission of data over an asynchronous communication medium is provided. A headend receives one or more bandwidths requests from one or more cable modems via upstream communication. A scheduler then combines one or more bandwidths requests from the same cable modem to create a single data burst bandwidth. The headend then grants the data burst bandwidth to the appropriate cable modem via downstream communication.

Abstract: A method and related computer program product of obtaining temporary conventional memory usage in BIOS. The method and program product comprises disabling processor interrupts, saving a predetermined amount of system memory to a temporary storage location outside system memory, using the predetermined system memory space for BIOS specific needs, restoring the predetermined amount of system memory from the temporary storage location to the predetermined system memory space, and then re-enabling the processor interrupts.

Abstract: During start-up of a circuit having a high voltage supply and a low voltage supply, a backup bias generator (BBG) is used to avoid burnout and exceeding a breakdown voltage. The high voltage supply is powered on before the low voltage supply. The BBG generates bias in response to the high voltage supply being powered on. Once the low voltage supply is powered on and is stable, the BBG is shut down so that it does not interfere with normal operation of the circuit. The circuit can be separated into high and low supply domains without breakdown issues during power start-up, allowing for power and area optimization.

Abstract: An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the summed signal and outputs a quantized output signal. A limiter receives the summed signal and outputs a limited summed signal. The limiter limits the limited summed signal to ?* (maximum value of input signal), ?>1. A second summer receives the limited summed signal and the output signal and outputs an error signal. A filter receives the error signal and outputting the feedback signal. Typically, 1.0<?<2.0, more preferably 1.4<?<1.6. The filter has a transfer function of H1(z)=2z?1?z?2.

Abstract: A system for spur cancellation comprises an input, an output, a memory, and a summer. A value corresponding to an energy level of a spur is stored in the memory. The summer is configured to receive an input signal from the input, to receive the value from the memory, to subtract the value from the input signal, and to convey an output signal to the output. The output signal is a difference of the value subtracted from the input signal.

Abstract: A multi-frequency clock stretching system is provided. The multi-frequency clock stretching system includes a stretch pulse generator that generates a stretch pulse signal and a multi-frequency clock generator that produces a set of different frequency clock signals in which the clock signal pulses of the set of different frequency clock signals can be stretched as a function of the stretch pulse signal. A data processing system is also provided that includes a data processing portion and a multi-frequency clock stretching system. When the data processing portion recognizes that a clock adjustment is needed, the data processing portion provides a control signal to the multi-frequency clock stretching system that stretches the pulses of clock signals serving as inputs to the data processing portion to better align the pulses and improve system performance.

Abstract: The accuracy of output power in a digital-to-analog converter (DAC) is critical in certain applications. When bi-CMOS technology is used to implement a DAC, a number of factors affect the gain accuracy of the DAC. The present invention provides a circuit architecture to reduce the variation in these factors to ensure the accuracy of the output power of a DAC. The architecture comprises a bandgap portion, replica circuit and a DAC. The bandgap portion of the architecture provides a constant voltage, while the replica circuit provide a correct current to drive the DAC.

Abstract: A semiconductor device that reduces the parasitic capacitance between a conductive trace and a substrate, and a method of fabricating the same. The semiconductor device includes a substrate, an insulator layer disposed upon the substrate, a conductive trace disposed upon the insulator layer, and an element disposed between the substrate and the conductive trace. A first capacitance exists between the conductive trace and the substrate and a second capacitance results between the conductive trace and the substrate due to the presence of the element. The second capacitance is in series with the first capacitance, thereby reducing an effective capacitance between the conductive trace and the substrate.

Abstract: A number of features for enhancing the performance of a cable transmission system, in which data is transmitted between a cable modem termination system at a headend and a plurality of cable modems located different distances from the headend, are presented. The power transmission level, slot timing, and equalization of the cable modems are set by a ranging process. Data is transmitted by the modems in fragmented form. Various measures are taken to make transmission from the cable modems robust. The upstream data transmission is controlled to permit multiple access from the cable modems.

Abstract: Multi-tuner receivers with cross talk reduction are disclosed. In one embodiment, a multi-tuner receiver with cross talk reduction includes a low noise amplifier, a set of interstage filters and a set of corresponding tuners. In an alternative embodiment, a multi-tuner receiver with cross talk reduction includes a passive splitter, a set of interstage filters and a set of corresponding tuners. The interstage filters can be low-pass, high-pass or band-pass filters depending on the particular frequency range of interest. Typical embodiments can have two or three tuners, however, the invention applies to multi-receiver tuners with more than three tuners. The multi-tuner receivers can be used within television, cable set top boxes and other devices that receive multiple video signals.

Abstract: A printed dipole antenna includes a metal trace having first type sections and second type sections, wherein currents within the first type sections substantially cancel and currents the second type sections are substantially cumulative.

Abstract: According to the present invention, the bandwidth of a TDD channel is increased where multiple slave devices communicate with a master device over the channel. According to an aspect of the present invention, the master device can increase channel bandwidth by utilizing available transmit slots that occur during receipt of a multi-slot packet from a slave device. For example, the master device receives a first packet at a first frequency from a first slave via the channel. The master determines whether the first packet is a multi-slot packet, and if so, transmits a second packet to a second slave via the channel at a second frequency different from the first frequency. The second packet is transmitted after receipt of the first packet, but prior to the end of the first packet.

Abstract: A system and method for detecting and removing tones from an incoming communications channel that may also carry other signals such as, for example, voice is disclosed which includes pre-detecting tones in a communication signal, processing the communication signal to invalidate the tones in response to the tone pre-detection, forwarding the processed communication signal across a network, validating the tone and forwarding tone-on signals across the network in response to the validation.

Abstract: A high Q on-chip inductor includes a primary winding and an auxiliary winding that is coupled to receive a proportionally opposite representation of an input of the primary winding. Further, the auxiliary winding has an admittance that is greater than the admittance of the primary winding thereby yielding an asymmetry in the admittances. As such, a push/pull mechanism is obtained in a 2-port system (e.g., 1st and 2nd nodes of the primary winding) that produces a large Q factor for an on-chip inductor.

Abstract: A plurality of CMTS devices are linked together and synchronized to facilitate communication between the respective CMTS devices and respective downstream cable modems. According to one embodiment of the invention, one of the CMTS devices is designated as a master device, and the other CMTS devices are designated as slave devices. The respective CMTS devices are connected to each other by means of a synchronization bus. The master CMTS device then generates and broadcasts a future time stamp value, which is received by the respective slave CMTS devices. When the time stamp counter in the master CMTS device reaches the transmitted value, a control signal is broadcast over the synchronization bus. The slave CMTS devices then retrieve the time stamp value and reset their respective local time stamp counters to the received value. In this manner, the CMTS devices are synchronized.

Abstract: An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel.

Abstract: A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port Serdes transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. The ring structure of the bus provides efficient communication between the logic core and the various data ports.

Abstract: A method and signal therfor embodied in a carrier wave for sending information from transmit stations to receive stations over a transmission medium of a frame-based communications network. The information is sent in transmit frames having a frame format comprising a fixed rate header, followed by a variable rate payload, followed by a fixed rate trailer. The fixed rate header includes a preamble. The preamble has a repetition of four symbol sequences for facilitating power estimation, gain control, baud frequency offset estimation, equalizer training, carrier sensing and collision detection. The preamble also includes a frame control field.

Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage.