Abstract: A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller (“DAC”), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially. The invention can be implemented as a Z/kZ ladder network, where k is a real number.

Abstract: A method and related computer program product for operating a computer system which in a preferred embodiment comprises, acquiring a digital image of a hardware element, storing the digital image, displaying the digital image in a software program and dynamically updating and displaying status information for hardware elements proximate to the digital image and allowing the user to dynamically change element status by interacting with the displayed image.

Abstract: Computer-implemented method and system for generating an optimized description of an arithmetic function comprising at least two of an addition, a multiplication, and a rounding operation to be carried out on a plurality of data bits in a plurality of registers of an electronic circuit, the method comprising the steps: obtaining a first description of the arithmetic function; decomposing the first description to obtain a second description comprising individual binary and logical operations on data bits, wherein the data bits are arranged to their proper place value, the second description being substantially arithmetically equivalent to the first description; obtaining a third description by parallelizing at least two of the binary and logical operations on the data bits in the second description; providing a forth description comprising operations for each data bit comprised in the third description in a hardware description language as the optimized description of the electronic circuit.

Abstract: A method and related computer program product for combining resources of multiple RAID controllers and managing them as a single entity, comprising searching the RAID controllers for the most appropriate version of the firmware to be executed, determining whether a more appropriate version of the firmware was previously loaded into system memory, unloading inappropriate versions of the firmware, loading the most appropriate version of the firmware and initializing all RAID controllers as a commonly managed entity having combined resources.

Abstract: A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller (“DAC”), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially.

Abstract: An on-chip differential inductor includes a 1st interwound winding having a substantially octagonal shape, or rectangular octagonal shape, and a 2nd interwound winding having a substantially octagonal shape, or rectangular octagonal shape, that is interwound with the 1st interwound winding. Both the 1st and 2nd interwound windings are on the same layer of the integrated circuit. Each interwound winding includes two nodes; one of node of each winding is commonly coupled to a reference potential. The other node of each winding is operably coupled to receive a respective leg of a differential signal.

Abstract: A multi-function interface includes a digital interface module and a configurable output impedance module. The digital interface module is operably coupled to pass a first type of input signal when the multi-function interface is in a first mode and operably coupled to pass a second type of input signal when the multi-function interface is in a second mode. The configurable output impedance module is operably coupled to the digital interface to provide a first output impedance when the multi-function interface is in the first mode and to provide a second output impedance when the multi-function interface is in the second mode.

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract: The present invention provides for handling data flow within a network device, which includes a cycle timing module, a division module, an assignment module, and an input device. The cycle timing module is configured to determine the cycle time needed to process a set of incoming data. The division module is configured to divide a serial shifting bus into a plurality of segments, wherein the serial shifting bus is included within the network to transfer the data. The assignment module is configured to assign a plurality of assembly lines to each segment, wherein each of the assembly lines is connected to the serial shifting bus. The serial shifting bus serially shifting the data until the data reaches end of the bus segment. The end of the serial bus segment is configured to transfer the data out of the serial shifting bus to a management information base processing unit.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The first IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes a portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface.

Abstract: An embedded ROM-based processor system including a processor, system memory, a programmable memory, a data selector and a patch controller. The system memory includes a read-only memory (ROM). The programmable memory stores patch information including patch code and one or more patch vectors. Each patch vector includes a break-out address from the ROM and a patch-in address to a corresponding location within the patch code. The data selector has an input coupled to the system memory and an output coupled to the processor. The patch controller is operative to compare an address provided by the processor with each break-out address to determine a breakout condition, and to control the selector to transfer the processor to a corresponding location within the patch code in response to a break-out condition. The programmable memory may be volatile memory, where the patch information is loaded from an external memory during initialization.

Abstract: Provided is a circuit to convert input CMOS level signals having a predetermined duty cycle to CML level signals having a higher duty cycle. The circuit includes two differential transistor pairs connected together. The two differential pairs are constructed and arranged to use gates of the associated transistors as inputs to receive and combine a number of phase shifted CMOS input signals. The combined CMOS input signal are converted to CML level signals which are provided as circuit outputs.

Abstract: A modulator circuit receives a modulator input signal and produces a mapper output signal. The modulator circuit includes a filter circuit that generates an output that is a function of the modulator input signal and of the mapper output signal. A quantizer receives the filter output signal and produces a quantized representation of the filter output signal. A mapper receives the quantizer output and generates the mapper output signal.

Abstract: A mixer for a radio transceiver includes a commutating mixer switch having a first differential input port coupled to a DC offset cancellation path. The first differential input port of the mixer switch includes a first terminal coupled to a first end of a first resistor and a second terminal coupled to a first end of a second resistor. Second ends of the first and second resistors are configured to receive a differential input signal. The DC offset cancellation path may provide a resistively coupled DC calibration signal for reducing the magnitude of DC offsets that may be present at the input of the mixer switch. The concept can be used for either image or non-image reject mixers.

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: An asymmetric digital subscriber line (ADSL) transceiver chip is provided that includes a single integrated circuit (IC) substrate to host the circuit and an analog front-end (AFE) configured to receive and transmit analog signals. The AFE has a dynamic range greater than about 85dB and the received analog signals have bandwidths of about 2 mega-hertz. The ADSL chip also includes a digital signal processor (DSP) configured for digital processing and including bypass capacitors configured to provide switching charge. The AFE and the DSP are formed on the single IC substrate.

Abstract: A mechanism and method for redefining an application specific integrated circuit's I/O bus structure in real-time. The mechanism includes an address map block, a state machine block, and a bus arbitration block. At initialization, the address map is configured to divide the address space into regions and type of bus structure. When an I/O access is requested by a client (e.g., CPU, DMA controller, etc.), the request is mapped into a region and type of bus structure by the address map block. The region and type of bus structure is used by the state machine. The state machine determines the syntax and protocol for the region and type of bus. The state machine signals the bus arbitration block to grant I/O bus ownership when it is available. Once ownership is granted, I/O bus pins are defined and access is granted.

Abstract: A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer receives an output of the first flip flop and outputs peak data. A second demultiplexer receives an output of the second flip flop and outputs zero data. A timing recovery circuit outputs phase control bits based on the zero data and the peak data. A first phase interpolator outputs the 0° clock based on the phase control signal. A second phase interpolator outputs the 180° clock based on the phase control signal. A phase register receives the phase control signal from the timing recovery circuit. The first and second flip flops can be D flip flops. The first and second phase interpolators adjust relative phases of the 0° clock and 180° clock based on the phase control signal.

Abstract: A low power supply band-gap current reference includes a 1st P-N junction device, a 2nd and P-N junction device, a 1st current source, a 2nd current source, a 1st resistor, a 2nd resistor, a 3rd resistor, an operational amplifier, and a current mirror. The 1st and 2nd P-N junction devices are operably coupled to the 1st and 2nd current sources, respectively. The 2nd P-N junction device is a larger device than the 1st P-N junction device. The 2nd resistor is operably coupled in parallel with the 1st P-N junction device and the 2nd resistor is coupled in series with the 2nd P-N junction device. The 3rd resistor is coupled in parallel with the series combination of the 2nd resistor and 2nd P-N junction device. The operational amplifier is coupled to control the 1st and 2nd current sources based on the voltage imposed across the 1st and 2nd resistors. The current mirror is operably coupled to mirror the current of the 1st and/or 2nd current source to provide a band-gap reference current.