Abstract: 16 QAM (Quadrature Amplitude Modulation) and 16 APSK (Asymmetric Phase Shift Keying) TTCM (Turbo Trellis Coded Modulation) with minimum bandwidth efficiency of 3 bit/s/Hz (bits per second per Hertz) using a rate 2/4 constituent encoder. Various encoder designs are presented that are operable to generate a signal whose modulation may vary as frequently as on a symbol by symbol basis while providing relatively very high throughput. Rate control sequences including RCs (Rate Controls), arranged in a period, govern the manner in which symbols of a signal are generated. The RCs correspond to various modulations that may each have a unique constellation and corresponding mapping. Different RCs may be included within a rate control sequence that correspond to 16 QAM, 16 APSK, QPSK (Quadrature Phase Shift Key), or even other modulation types. In addition, 1 or more uncoded bits may be used to generate the symbols of the coded signal.

Abstract: Methods and systems for increasing gain for an electric circuit may include receiving an input differential signal at a first configured pair of transistors and a second configured pair of transistors. The first and second configured pair of transistors may be inductively loaded. The first configured pair of transistors may be self-biased via the inductive loading. DC current may be generated via the second configured pair of transistors. The first and/or the second configured pair of transistors may be configured as input transconductors. A pair of inductors may be configured for the inductive loading and the configured pair of inductors may be tapped for the self-biasing. If the first configured pair of transistors comprises NMOS transistors, then the second configured pair of transistors may comprise PMOS transistors.

Abstract: Classification of packets into flows is an inherent operation performed by networks that support enhanced services. To support multiple-dimensional packet classification, a packet classification system is provided to select representative bits from a packet to look up a set of rules. The per-flow classification works with a large set of rules, where each rule comprises of multiple fields and also allows fast dynamic variation in the rule set. A lookup process includes a simple and finite set of instructions that can be efficiently implemented as pipelined hardware and support very high packet arrival rates.

Abstract: Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of a cryptography accelerator coupled with a processor. Hardware normalization techniques are applied to data prior to cryptography processing. Context circuitry tracks the shift amount used for normalization. After cryptography processing, the processed data is denormalized using the shift amount tracked by the context circuitry.

Abstract: A system is provided for correcting start-up deficiencies in an amplifier. The system includes a comparing device configured to (i) receive a second circuit node voltage and a reference voltage as inputs, (ii) compare the received second circuit node voltage and the reference voltage, and (iii) produce a compensating voltage signal based upon the comparison. Next, an active device has a control terminal connected to an output port of the comparing device and is configured to receive the compensating voltage signal. The active device also includes an output terminal connected to the control terminal of the second active device, and a common terminal connected to a first circuit node. Another active device has a control terminal connected to the output port of the comparing device and is configured to receive the compensating voltage signal. The other active device also has an output terminal connected to the control terminal of the first active device, and a common terminal connected to the first circuit node.

Abstract: In digital-to-analog conversion systems, a method and system for increased effective resolution in an N-bit DAC are provided. Additional resolution may be provided in an N-bit DAC by increasing the number of periods that an N-bit PWM may utilize to generate an output train of pulse widths with a desired duty cycle. An increased resolution bits parameter may correspond to the additional bits necessary to provide the increased resolution. An iterative process by which a desired value is converted into a sequence of N-bit control words may be based on a desired analog value and the increased resolution bits parameter. In addition to higher resolution, most of the output pulse AC energy is concentrated at the N-bit PWM basic frequency and above, allowing for simpler analog filtering of the pulse width modulated signal.

Abstract: A method and apparatus are disclosed for easily reconfiguring a scan chain test of a subset of scan blocks within a digital integrated circuit chip. To mitigate timing violations in the scan test of scan chains, alternative embodiments to implement a transfer of scan data to a next scan block are implemented.

Abstract: A network controller having a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter including a predictive time base generator; and a management bus controller adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus. The management bus controller is adapted to employ an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, a Simple Network Management Protocol (SNMP), or a combination thereof. The network controller also includes a 10/100/1000BASE-T IEEE Std. 802.

Abstract: Provided is a system and method for converting digital data audio data audio data that has a predetermined input sample rate, into an analog data signal. A system includes a digital to analog converter (DAC) including a digital processing portion configured to receive as an input the digital audio data and timing information, the timing information being representative of a time base of the input sample rate. The digital processing portion is similarly configured to digitally process the digital audio data and the timing information to produce serialized output data. The DAC also includes an analog processing portion configured to convert serialized data to an analog format. The digital processing portion operates in accordance with at least one clock having a corresponding clock rate wherein the corresponding clock rate is unrelated to the input sample rate.

Abstract: A method and system for allocating an initial maintenance request (IMR) for an upstream channel in a communications system, wherein the communication system includes a headend and at least one remote device associated with the channel. A first propagation delay from the headend to the remote device having the greatest delay is determined. Likewise, a second propagation delay from the headend to the remote device experiencing the least delay is determined. The IMR is then defined to be shorter than the first propagation delay and at least as long as the difference between the two propagation delays. The starting point of the IMR is established by modifying the clock output of the headend. A modification value is added to the headend clock output. The modification value corresponds to a time interval that can be as long as the propagation delay from the headend to the remote having the shortest delay.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A varactor-based ring oscillator to produce an output signal and method therefore are disclosed. The ring oscillator includes a first phase shift circuit having a first pole. The ring oscillator also includes a second phase shift circuit having a second pole and a third phase shift circuit having a third pole. The output of the third phase shift circuit is cross-coupled to the input of the first phase shift circuit. A phase shift circuit of the ring oscillator includes a pole that has a varactor and generates phase shift for the phase shift circuit. The varactor can be adjusted or varied to tune, the phase shift, the phase shift circuit and the frequency of the oscillator. If the varactor is in the final phase shift circuit of the oscillator, the varactor is coupled to a diode that supplies voltage to the varactor. A voltage control signal is applied to the pole, and to the oscillator, to generate the output signal having a specified frequency.

Abstract: A logic circuit includes an interface and an error detection unit. The interface is configured to receive and transmit a data stream, wherein the data stream includes at least one of a variable length format packet or burst and a fixed length format packet or burst. The error detection unit is configured to detect an error detection code error when a misalignment occurs within the data stream by recursively calculating parity terms.

Abstract: A video and graphics system provides square graphics pixels to blend images having 640×480 pixels, such as graphics images provided by some set top boxes and intended to be displayed at a 12.27 MHz display sample rate, with images having 704×480 pixels, such as ITU-R 601 compliant images such as NTSC SDTV images, having oblong pixels and displayed at a 13.5 MHz display sample rate. A sample rate converter including a multi-phase-multi-tap filter is used to generate square pixels. The multi-phase-multi-tap filter provides a good balance of sharpness, smoothness, anti-aliasing and reduced ringing. The multi-phase-multi-tap filter can also be used to convert images having 320×480 pixels to images having 704×480 pixels. The multi-tap filter can be used for scan rate conversion of graphics or video images for HDTV or SDTV applications.

Abstract: Circuits and methods to enhance scan testing by controlling clock pulses that are provided to memory devices within an integrated circuit are provided. An integrated circuit is provided that includes a scan testing clock control circuit and a memory bypass enable contact point. The scan testing clock control circuit enables control of a clock input signal to one or more memory devices within the integrated circuit. In one embodiment the scan testing clock control circuit includes a latch, and two AND gates. A scan test mode input and a memory bypass enable input are used to determine whether the memory will be permitted to receive a clock signal. Methods for scan testing using a scan testing clock control circuit are also provided.

Abstract: Aspects of the invention for converting interlace formatted video to progressive scan video, may include a color edge detector block (306) adapted to determined edges in interlaced formatted video. A threshold and gain processor block (308) coupled to the color edge detector block (306) may be adapted to quantify a likelihood of motion for each pixel comprising at least a portion of the interlaced scanned video using a motion value. A binder block (310) coupled to the threshold and gain processor block (308) may be configured to combine the motion value for each component of a luminance and chrominance of each of the pixels. A resampler block (314) may be coupled to the binder to determine an actual pixel value. The resampler block (314) may include at least one of a vertical and a horizontal filter adapted to determine an actual value of each of the pixels in at least a portion of the interlaced scanned video.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.

Abstract: Systems and methods that protect transport stream content are disclosed. The system may include a first module and a second module, the first module having a common interface. The second module is coupled to the first module via the common interface. In one embodiment, the first module is a set top box, and the second module is a conditional access card. In one example, the first module demodulates an incoming transport stream, copy protection encrypts the demodulated transport stream and passes the copy protection encrypted transport stream to the second module via the common interface. The second module copy protection decrypts the transport stream received from the first module, conditional access decrypts at least some of packets of the transport stream that were conditional access encrypted, copy protection encrypts the transport stream and passes the copy protection encrypted transport stream to the first module via the common interface.

Abstract: A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.

Abstract: An LED interface circuit provides connection options for one or more types of LEDs. In an embodiment, the circuit includes an input node that receives an LED control signal, and an output that has a first output node, and a second output node. A driving circuit is disposed between the input header and the output. The driving circuit has a non-inverted input node and an inverted output node. In an embodiment, the inverted output node is capable of sinking current. The non-inverted input node is coupled to the input header and to the first output node, while the inverted output node is coupled to the second output node. The output of the LED interface circuit is capable of driving a plurality of different types of LED displays.