Abstract: A direct conversion tuner down-converts television signals, cable signals, or other signals directly from an RF frequency to an IF frequency and/or baseband, without an intermediate up-conversion step for image rejection. The direct conversion tuner includes a pre-select filter, an amplifier, an image reject mixer, and a poly-phase filter. The pre-select filter, amplifier, and the image reject mixer can be calibrated to provide sufficient image rejection to meet the NTSC requirements for TV signals. The entire direct conversion tuner can be fabricated on a single semiconductor substrate without requiring any off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: Embodiments of the invention enable generation of an IF output signal amplitude that is less sensitive to process voltage and temperature than conventional transmitters.

Abstract: Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.

Abstract: A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a substrate. A portion of the first metal layer is utilized as the lower plate of the MIM capacitor. An etch stop dielectric layer is used during etching of subsequent layers. A portion of an etch stop layer is not removed and is utilized as the insulator for the MIM capacitor. A second copper or copper alloy metal layer is later formed on the substrate. A portion of the second metal layer is utilized as the upper plate of the MIM capacitor.

Abstract: The present invention relates to a replica network for linearizing switched capacitor circuits. A bridge circuit with a MOSFET resistor disposed in a resistor branch of the bridge circuit is provided. A noninverting terminal of an operational amplifier is connected to a first node of the bridge circuit and an inverting terminal of the operational amplifier is connected to a second node of the bridge circuit. The second node is separated from the first node by another node of the bridge circuit. An output of the operational amplifier is provided to a gate terminal of the MOSFET resistor and to the gate terminal of the MOSFET switch in a switched capacitor circuit, thereby controlling the resistance of the MOSFET switch so that it is independent of the signal voltage. In this manner, the replica network of the present invention linearizes the switched capacitor circuit. In this manner, the replica network of the present invention linearizes the switched capacitor circuit.

Abstract: Methods and circuitry reduce adverse impacts of intermodulation and optimize performance of integrated circuits that include two or more oscillator circuits on the same chip. In one embodiment, intermodulation between voltage-controlled oscillators (VCOs)in the receiver and transmitter paths of a transceiver is reduced by adjusting relative power of the VCOs and/or bandwidths of the phase-locked loops (PLLs). The invention measures the injection lock frequency range of the VCOs based on which transmitter and receiver VCO power and loop bandwidths are adjusted.

Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential, and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to coupl

Abstract: A network switch for network communications includes at least one data port interface supporting a plurality of data ports transmitting and receiving data. A CPU interface is configured to communicate with a CPU, and an internal memory communicates with the at least one data port interface. A memory management unit is provided for communicating data from at least one data port interface and the memory. A communication channel is provided, for communicating data and messaging information between the at least one data port interface, the memory, and the memory management unit. The configuration of the network switch also includes a fast filtering process, with the fast filtering processor filtering packets coming into the at least one data port interface. Selective filter action is taken based upon a filtering result.

Abstract: A network device includes a first switch, a second switch, address resolution logic (ARL), and a CPU. The first and second switch having a groups of ports which are a subset of the plurality of ports and are numbered by a different numbering schemes. The CPU coupled to the first switch and the second switch and configured to control the first switch, the second switch, and the ARL. A first link port of the first group of ports is coupled to a second link port of the second group of ports. The ARL is configured to perform address resolution based on the first and second numbering schemes such that when the first network port a data packet received at the first network port destined for the second network port is directly routed from the first network port to the second network port.

Abstract: A preprocessor system (10) reduces random noise in video pixels by providing a memory (19) arranged to store first pixels processed during a first time period. A motion detector (300) responds to differences between the first pixels and second pixels processed during a second time period after the first time period to generate corrected motion signals. A first filter (100) generates first filtered values in response to the differences and the corrected motion signals. An impulse detector (244) generates control signals in response to detection of impulses, and an impulse reducer (250) generates second filtered pixel values in response to the first filtered values and the control signals.

Abstract: A system for periodic noise avoidance including a timing discriminator receiving an input signal from a communications channel. The input signal includes data packets and empty slots with periodic noise. The timing discriminator outputs a first error measurement of periodic noise width and a second error measurement of periodic noise position. A first loop filter inputs the first error measurement and outputs a width of the empty slots. A second loop filter inputs the second error measurement and outputs a frequency of the periodic noise. An oscillator inputs the width of the empty slots and the frequency, and outputs an empty slot waveform to the timing discriminator.

Abstract: A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. The damping circuit may be a low pass filter. The buffer may be used in an interface circuit that produces an output signal from an input signal and controls the level of the output signal.

Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.

Abstract: An apparatus for maintaining synchronization with a plurality of asynchronous communication links includes a first counter that generates a first local network clock, and a second counter that generates a second local network clock. The apparatus also includes an offset controller coupled with the first counter and coupled with the second counter, the offset controller configured to load a current network clock value of a first network clock of a first communication link into the first counter, and to load a current network clock value of a second network clock of a second communication link into the second counter. The apparatus further includes a drift controller coupled with the first counter and with the second counter, the drift controller configured to correct a drift between the first local network clock and the first network clock and to correct a drift between the second local network clock and the second network clock.

Abstract: A sigma-delta modulator includes a summing junction that receives an input signal. A plurality of integrators are arranged in series, the integrators output an integrated signal value to a multi-input quantizer. The multi-input quantizer has a plurality of comparators each with switched capacitor inputs. The multi-input quantizer outputs a quantized signal to a multi-bit feedback DAC that drives the summing junction.

Abstract: A method and related computer program product of preventing write corruption in a redundant array in a computer system, comprising detecting a write failure from a calling application to at least one disk of the redundant array, writing failure information to non-volatile storage; returning an I/O error to the calling application; reading the failure information from the non-volatile storage during the next system reboot; and reconfiguring the array to eliminate the failed disk.

Abstract: A board has connectors for interfacing to external devices mounted at a rearward edge of the board, minimizing the need to make connections and route connecting cables in the space between the board and adjacent boards installed in a computer system. In one embodiment the board is a RAID controller board and comprises a first edge portion configured to mate with a housing of a computing device, a second edge portion adjacent to the first edge portion and having an edge connector to interface the board with a corresponding slot in a computing device, at least one connector mounted proximate to a third edge portion located opposite the first edge and adapted to provide a data transfer connection with at least one compatible storage device, and a control circuit connected to the edge connector and at least one connector on the board to control the operation of the storage device.

Abstract: A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of double-balanced IQ mixers. The double-balanced mixers include cross-coupled PMOS devices that dynamically inject current at zero-crossing points to cancel out tail currents in the mixers. Also, methods of operating the above-discussed receiver and receiver front end.

Abstract: A process of maintaining access information between wireless hotspots is disclosed. A logon request from a wireless portable device is received by a first access point of a first wireless hotspot and use of the first access point by the wireless portable device is authenticated to establish an access session. Then, information related to the access session is passed to a shared register accessible by a plurality of wireless hotspots and the access session is monitored to determine whether a disconnect by the wireless portable device occurs. Additionally, when the wireless portable device moves from a coverage area of the first wireless hotspot to one coverage area of one of the plurality of wireless hotspots, the information related to the access session may be used to facilitate access to the one of the plurality of wireless hotspots by the wireless portable device.

Abstract: A single integrated circuit includes logic that supports 10BASE-T, 100BASE-T and 1000BASE-T transceiver functionality. The invention implements power management techniques by placing unused functionality in sleep mode. When the functionality is required later, then that functionality may be awakened again and used as required for the particular situation. A processor is able to interact with the media access controller (MAC), and the MAC then communicates with the physical layer (PHY). The invention is adaptable to various devices that are capable to operating using 10BASE-T, 100BASE-T and 1000BASE-T, even those the PHY of these devices may be somewhat different.