Abstract: A method of handling data packets in a network switch is disclosed. The method includes placing incoming packets into an input queue and applying the input data packets to an address resolution logic engine. A lookup is performed to determine whether certain packet fields are stored in a lookup table; and the result of the lookup is also examined to determine if it provides a trunk group ID for a particular data packet of the input data packets. When the lookup provides a trunk group ID, the trunk group ID is used to determine an egress port and the particular data packet is forwarded to the egress port. Alternatively, the packet is discarded, forwarded, or modified based upon the result of the lookup, where the lookup does not provide a trunk group ID. A network switch using the method is also disclosed and methods directed to mirroring of data packets are also disclosed.

Abstract: An IQ receiver includes an estimator/compensator module to determine and correct IQ mismatch errors between the I and Q channels of the IQ receiver. The estimator module determines a phase compensation factor C1 and an amplitude compensation factor C2 based on a calibration signal that is injected into the analog front-end of the IQ receiver. A compensator module applies the phase correction factor C1 and the amplitude correction factor C2 to the baseband output of the Q channel in order to reduce any phase or amplitude errors between the I and Q channels. The estimator module and the compensator module can be efficiently implemented in a digital state machine, or processor, including a digital signal processor.

Abstract: A communication line having a plurality of twisted wire pairs connects a plurality of transmitters, one transmitter at each end of each twisted wire pair, with a plurality of receivers, one receiver at each end of each twisted wire pair. Each receiver receives a combination signal including a direct signal from the transmitter at the opposite end of the twisted wire pair with which the receiver is associated and a plurality of far-end crosstalk (FEXT) impairment signals, one from each of the remaining transmitters at the opposite end of the communications line. A plurality of FEXT cancellation systems, one associated with each receiver, provides a replica FEXT impairment signal. A device associated with each receiver is responsive to the combination signal received by the receiver and the replica FEXT impairment signal provided by the FEXT cancellation system associated with the receiver for substantially removing the FEXT impairment signals from the combination signal.

Abstract: A variable gain amplifier includes circuit elements that may be partially powered down during transmit modes of operation and that may be powered back up whenever the radio transceiver receives a data packet within a specified settle time even for high throughput RF communications. The radio transceiver circuit may be powered down even in high throughput communications during a transmit mode to reduce power consumption. A DC offset cancellation block is operably coupled to the variable gain block to substantially remove any DC offset from the amplified output. The variable gain amplifier is further able to provide DC offset cancellation within the required settle time by holding the offset value during a dormant mode of operation.

Abstract: Presented herein are system(s), method(s), and apparatus f or detecting and recovering from false synchronization. When incorrect checksums are encountered, false synchronization and general noisy considerations are distinguished as causes of the incorrect checksums by examining the header data. For example, in one embodiment, a count can be kept and false synchronization and noisy conditions can be distinguished based on the number of detected null packets. In another embodiment, a count of detected PAT packets can be kept, and false synchronization and noisy conditions can be distinguished based on the number of detected PAT packets. In another embodiment, continuity information can be monitored and false synchronization and noisy conditions can be distinguished based on the continuity of the data packets.

Abstract: Methods and systems for fully differential frequency doubling include receiving a differential input signal having a first frequency, generating a non-inverted or positive output signal having twice the frequency of the input signal, and generating an inverted or negative version of the positive output signal. The positive and negative output signals form a fully differential output. The duty ratio of the output signals substantially matches a duty ratio of the input signals. Fully differential frequency doubling can be implemented with NMOS and/or PMOS devices. The invention further provides optional circuitry for increasing an output signal level.

Abstract: A differential multiplexer includes a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a positive input signal and a negative input signal, and outputs positive and negative output signals. Each multiplexing circuit includes first, second, third and fourth transistors. The first and second transistors input the positive input signal. The third and fourth transistors input the negative input signal. Outputs of the first and third transistors are connected to the positive output signal. Outputs of the second and fourth transistors are connected to the negative output signal. The positive and negative output signals are controlled using gate voltages on the first and fourth transistors. The second and third transistors are turned off when the differential multiplexer is in use. The transistors are cross-coupled to make leakage between the positive and negative input signals common mode in the positive and negative output signals.

Abstract: A network switch for network communications includes a first data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is configured to communicate with a CPU, and an internal memory communicates with the first data port interface and the second data port interface. A memory management unit is provided, including an external memory interface, for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, for communicating data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit.

Abstract: An integrated VCO having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention an integrated VCO. The VCO comprises, a substrate, a VCO tuning control circuit responsive to a VCO state variable that is disposed upon the substrate, and a VCO disposed upon the substrate, having a tuning control voltage input falling within a VCO tuning range for adjusting a VCO frequency output, and having its tuning range adjusted by the tuning control circuit in response to the VCO state variable.

Abstract: A method for encapsulating and decapsulating information into a data packet being transmitted through a plurality of switches. The method has the steps of receiving a data packet in a first switch for transmission to a second switch and encapsulating information into a field of said data packet so that the information, when encapsulated into the data packet, does not increase the size of the data packet. The method also has the steps of transmitting the data packet having the information encapsulated in the data packet to the second switch and receiving the data packet having the information encapsulated in the data packet in the second switch. The final step is the step of decapsulating the information encapsulated in the data packet.

Abstract: Digital communications devices having high-speed add-compare-select circuits, and methods for designing the same. The add-compare-select circuits include logic segments separated by delay devices. The separation of the logic segments allows for pipelining of the add-compare-select processes and advantageous circuit retiming. The pipelining and advantageous circuit retiming permit the digital communications devices to be clocked at higher rates than similar digital communications devices having conventional add-compare-select circuits.

Abstract: A clock generator includes an active oscillator portion that generates an oscillating signal having a frequency determined by a resonator, such as a crystal or other type of resonator. A filter or delay module filters or delays the oscillating signal to generate a second oscillating signal that has a DC component that matches that of the original oscillating signal. A comparator then compares the original oscillating signal with the filtered or delayed oscillating signal to determine the amplitude cross points. In other words, the comparator determines where the amplitude of the original oscillating signal crosses that of the filtered or delayed oscillating signal, and generates a square wave pulse at the amplitude cross points. Since both compared signals have a common DC component then the amplitude cross points will be equally separated in time, which produces an output oscillating signal with a 50% duty cycle.

Abstract: A transmitter includes a detection element to determine when a current power requirement of a communication link is less than the standard transmit power. The current power requirement may be determined by a current operation condition of the communication link, for instance. The transmit power of the transmitter may be set to be less than the standard power in any of a variety of ways. For example, a center tap voltage of the transmitter may be reduced. In another example, a class of operation of the transmitter may be changed. In yet another example, the transmitter may include a current mirror having a plurality of diode-connected transistors coupled in parallel, thereby reducing the current at output terminals of the transmitter. Reducing the current at the output terminals decreases the output power of the transmitter, which may reduce the power consumed by the transmitter.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The display engine processes graphics images formatted in any one of a plurality of formats including a color look up table (CLUT) format. A color look-up (CLUT) table loading mechanism preferably facilitates the transfer of real-time CLUT table data during graphics composition. The loading mechanism may be triggered by a window descriptor that contains a color look-up table load command.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A motion detector (300) detects motion of images represented by video pixels. A first motion detector (320) is arranged to generate first motion signals (S) representing detected motion of images represented by the pixel values. A second motion detector (360) is arranged to modify the first motion signals to generate corrected motion signals (S?) in response to the relationship of a pixel being processed to a change of motion of one or more of the image in the vertical direction. The second motion detector also modifies the first motion signals in response to the value of the pixel being processed.

Abstract: Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

Abstract: A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplary embodiment of the present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern. In order to facilitate the checking process, signature analysis is utilized.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: Methods and systems for communicating on a wireless channel are provided which enable subscribers that share the channel to transmit using different modulation schemes. The modulation scheme used by each subscriber is assigned to the subscriber by a wireless access termination system. The modulation scheme assigned to a subscriber by the wireless access termination system is determined based on measurements of the quality of signals received from that subscriber. In one embodiment, the invention includes a transmitter and a receiver. The receiver is capable of transmitting data using one of a number of encoding and symbol constellation configurations. The receiver is also capable of receiving a first signal. Receiving the first signal causes the transmitter to transmit a second signal using a specified encoding and symbol constellation configuration.