Abstract: A system may include at least a first agent and a second agent, and the first agent may be coupled to receive a block signal generated by the second agent. The block signal is indicative of whether or not the second agent is capable of participating in transactions. The first agent initiates or inhibits initiation of a transaction for which the second agent is a participant responsive to the block signal. The system may include additional agents, each configured to generate independent block signals. Other implementations may share block signals among two or more agents. For example, a memory block signal indicative of memory transactions being blocked or not blocked and an input/output (I/O) block signal indicative of I/O transactions being blocked or not blocked may be employed. In yet another implementation, a first agent may provide separate block signals to other agents.

Abstract: Provided is system for an improved programmable gain amplifier (PGA). The system includes an amplifier and a first gain control mechanism. The first gain control mechanism includes a circuit input port and is positioned along a feedback path of the amplifier. The first gain control mechanism is configured to (i) receive an input signal and (ii) moderate gains applied to the received input signal, the applied gains including gain values of greater than or equal to one. A second gain control mechanism is coupled to the first gain control mechanism and is integrated with a function of the amplifier. The second gain control mechanism (i) provides gain values of less than one and (ii) decreases a feedback factor of the amplifier when the gain values are provided having values of less than one.

Abstract: The present invention is directed to systems and method of controlling clock signals during scan testing integrated circuits. The methods and systems provide efficient at-speed scan testing while minimizing the external pins on an integrated circuit dedicated to scan testing clock sources. A clock control circuit is disclosed that includes a scan test control module for permitting a clock signal to be transmitted and a scan test clock decision module for determining whether a clock signal should be permitted to be transmitted. An integrated circuit is disclosed that includes a set of clock control circuits. Embodiments of a scan test control module are provided that can process decoder inputs, ATPG inputs or both. A method is provided that can be used, for example, by an ATPG tool to efficiently provided at-speed scan testing while minimizing external pins dedicated to scan testing clock sources.

Abstract: A system and a method are presented for detecting the presence of at least one clock signal of a defined clock frequency applied to at least one input port of an integrated circuit system, wherein the a first number M of clock pulses related to the at least one clock signal within a predefined cycle period is counted and the counted first number M of clock pulses is compared with a reference number. Depending on the result of the comparison the presence of the at least one clock signal is detected or not.

Abstract: An environmental-compensated oscillator includes a reference clock waveform generator; a phase locked loop receiving the reference clock waveform and outputting a phase locked clock waveform; and a sensor outputting a voltage corresponding to an environmental parameter of the generator. The voltage is used by the PLL to compensate the phase locked clock waveform. The PLL includes a phase detector, a charge pump coupled to an output of the phase detector, a low pass filter coupled to an output of the charge pump, a voltage controlled oscillator (“VCO”) coupled to an output of the low pass filter, and a feedback path coupled between an output of the VCO and the phase detector, wherein the feedback path includes a phase rotator capable of fine tuning an output frequency of the VCO responsive to a frequency of an input clock. An accumulator is coupled to the phase rotator and supplies the input clock to the phase rotator. The phase rotator finely tunes the VCO output frequency.

Abstract: A network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far end data termination devices via a hybrid fiber coaxial network and a cable modem termination system. The described network gateway combines a QAM receiver, a transmitter, a DOCSIS MAC, a CPU, a voice and audio processor, a voice synchronizer, an Ethernet MAC, and a USB controller to provide high performance and robust operation. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A method and apparatus for an image canceling digital-to-analog converter is disclosed. Up-sampling and noise shaping is used to produce a stream of digital sample values at a relatively higher sampling rate than the sampling rate of the digitized input samples, each higher sampling rate sample having fewer bits than the original samples. The higher sampling rate stream is then distributed for sequential conversion by multiple digital-to-analog converters each operating at a lower sampling rate. The outputs of the converters are then combined to form a combined output signal. Most spectral images normally observed in a standard or conventional DAC are attenuated in the combined output signal of an embodiment in accordance with the present invention. Any spectral images that remain are further from the signal of interest, permitting the use of lower cost filtering.

Abstract: A power supply and switching technique is provided that utilizes a first battery and a second battery to charge a load. The power supply includes a first controlled power switch coupled to the first battery and the load, a second controlled power switch coupled to the second battery and the load, and a power controller coupled to the first controlled power switch, the second controlled power switch and the load. The power controller monitors the voltage and the load and causes a charge to be applied to the load when the load voltage is not a predetermined voltage. The power controller causes a charge to be applied to the load by selectively closing the first controlled power switch, thereby providing a charge from the first battery to the load, and/or selectively closing the second controlled power switch, thereby providing a charge from the second battery to the load. A similar switching technique may be used to recharge the first and second battery by alternately coupling them to an external power source.

Abstract: Method and apparatus for Min star calculations in a Map decoder. Min star calculations are performed by a circuit that includes a first circuit that performs an Min(A,B) operation simultaneously with a circuit that calculates a ?log(1+e?|A?B|) value. The sign bit of the A?B calculation is used to select whether A or B is a minimum. The A?B calculation is also used to select either ?log(1+e?|A?B|) or ?log(1+e?|B?A|) as the correct calculation. In order to hasten the selection of either ?log(1+e?|A?B|) or ?log(1+e?|B?A|) as the correct calculation the apparatus does not wait for the A?B calculation to complete. Any bit of the A?B calculation between the third bit and final (sign bit) can be used for the selection. If an incorrect value is selected a log saturation circuit may correct the value.

Abstract: A method and apparatus for detecting and classifying RF impairments on the upstream path of a communication system is provided. The detection system detects frequencies with common path distortion impairments, and a system manager avoids transmission over those frequencies or adapts transmissions accordingly. Subsequently, periodic impairments on the upstream path are detected. Detection of periodic impairments triggers the system manager to schedule no traffic during impairment periods, schedule low priority traffic during impairment periods, and/or adjust the physical layer parameters of traffic transmitted during an impairment period in order to increase robustness only when necessary. Finally, non-periodic or random impairments are detected on the upstream path and global parameter changes are made to adapt to non-predictable impairments. Each of the impairment types is then further classified to assist an operator of the system in determining the physical source of the impairment.

Abstract: Efficient address generation for interleaver and de-interleaver. The present invention performs interleaving and de-interleaving, at opposite ends of a communication channel, by employing an efficient address generation scheme that is adaptable across a wide variety of applications and platforms. The present invention is particularly applicable to communication channels that exhibit a degree of bursty type noise. By employing interleaving and de-interleaving at the opposite ends of the communication channel, the present invention is able to offer a degree of protection against data corruption that may be caused within the communication channel. The present invention allows convolutional interleaving and de-interleaving operation on a code word by code word basis. The present invention provides for very efficient address generation for RAM based convolutional interleaving and de-interleaving.

Abstract: A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: A method and system for increasing the efficiency of providing bandwidth for voice traffic to a data provider via asynchronous communication mediums is provided. This is generally accomplished by not transmitting any data during the silence periods and playing out background noise (i.e., comfort noise) at the other end, to obtain significant bandwidth savings.

Abstract: The present invention is directed to a method for debugging scan testing failures of integrated circuits. The method includes identifying good and bad scan paths among a set of scan paths. A scan path is bad if it is not producing any output. A scan path is good if it is producing a correct output. A clock set is generated for each scan path. The clock set includes all clock elements whose outputs impact the scan path. A union of the scan path clock sets for the bad scan paths is created. Good clock elements are removed from the union. A clock element is presumed to be good if it is associated with a good scan path. Clock elements remaining within the union of clock sets for the bad scan paths are analyzed to determine the source of errors. In one embodiment, multiple input clock elements in all bad scan paths are analyzed first, followed by analysis of single input clock elements in all bad scan paths and followed by analysis of any other clock elements in any of the bad scan paths.

Abstract: A hierarchical parallel pipelined circuit includes a first stage with a plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A second stage includes a second plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A multi-frequency, multi-phase clock clocks the first and second stages, the multi-frequency, multi-phase clock providing a first clock having a first frequency having either a single or plurality of phases, and a second clock having a second frequency having a plurality of phases. A first phase of a plurality of phases is phase locked to the first phase of the first clock. The clock frequency multiplied by the number of parallel devices in each stage is the throughput of the circuit and is kept constant across the stages.

Abstract: A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a MOSFET and applying this replicated voltage to the body terminal. In this manner, the effect of the body transconductance, at high frequencies, becomes a function of the ratio of the well-to-substrate capacitance of the MOSFET to the sum of the well-to-substrate capacitance and the source-to-body capacitance of the transistor. At high frequencies, the biasing scheme mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET by contributing a negative half plane zero to the transfer function of the feedback network, and reduces the power consumed by the gain boosting amplifier.

Abstract: A method of handling data packets in a network switch is disclosed. The method includes placing incoming packets into an input queue and applying the input data packets to an address resolution logic engine. A lookup is performed to determine whether certain packet fields are stored in a lookup table; and the result of the lookup is also examined to determine if it provides a trunk group ID for a particular data packet of the input data packets. When the lookup provides a trunk group ID, the trunk group ID is used to determine an egress port and the particular data packet is forwarded to the egress port. Alternatively, the packet is discarded, forwarded, or modified based upon the result of the lookup, where the lookup does not provide a trunk group ID. A network switch using the method is also disclosed and methods directed to mirroring of data packets are also disclosed.

Abstract: A multi-tone modem processes an input data stream 10 and uses an inverse Fourier transform 24 to produce a stream of multi-tone symbols 26 fed to an analogue front end 146. A model 32 models the subsequent processing in the analogue front end 146 and outputs a control signal 184 that controls the analogue front end 146 accordingly.

Abstract: Inter-device adaptable interfacing clock skewing. The invention is operable in either one of both of a transmit mode and a receive mode to perform skewing of a transmitted and/or a received signal. The operational parameters including frequency and phase may be determined during auto detect/auto negotiation, they may be programmed externally, or they may be user selected in various embodiments. A device may include a clock generator, one or more divider, and one or more delay cells internally to the device. If desired, a high frequency clock is generated within the device and then divided down to generate the appropriate clock signal that supports the communication and interaction between multiple devices. Registers and/or pins may be used to select the clock frequency and phase of output clock signals. The present invention supports multiple Ethernet protocols between multiple devices including 10BaseT, 100BaseT, and 1000BaseT.