Abstract: A method and apparatus are disclosed for conditionally enabling/disabling PCI power management in a computer-based system employing a central resource and an operating system. Non-CLKRUN# compatible PCI devices in the system are identified and whether or not the non-CLKRUN# compatible PCI devices are enabled is determined. The CLKRUN# support capability of the central resource, if available, is enabled or disabled based on, at least in part, the established status of the non-CLKRUN# compatible PCI devices. If enabled, PCI power management is provided by the CLKRUN# support capability according to the PCI CLKRUN# protocol for all CLKRUN# compatible PCI devices present in the computer-based system.

Abstract: An impulse-reducing module (200) reduces random noise in video pixels by providing an impulse detector (244) and an impulse reducer, such as a median filter (250). The impulse detector (244) generates filter control signals in response to detection of impulses, and the median filter (250) generates filtered pixel values in response to the filter control signals. The control signals set the median filter to a plurality of filter operating modes.

Abstract: Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of parallel connected resistors, each set corresponding to one of the impedance devices on the IC. Each set also includes two or more parallel resistor paths, each resistor path including two or more cascaded resistors and has a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device. Finally, the method includes configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed on the IC.

Abstract: A method and a system for providing an input signal from a multiple decision feedback equalizer to a decoder based on a tail value and a subset of coefficient values received from a decision-feedback equalizer. A set of pre-computed values based on the subset of coefficient values is generated. Each of the pre-computed values is combined with the tail value to generate a tentative sample. One of the tentative samples is selected as the input signal to the decoder. In one aspect of the system, tentative samples are saturated and then stored in a set of registers before being outputted to a multiplexer which selects one of the tentative samples as the input signal to the decoder.

Abstract: A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed.

Abstract: As additional channels are added to a communication system for applications, such as standard density (SD) and eventually high density (HD) Video on Demand (VOD), additional capacity can be realized by reducing the time required to transmit content. A reduction of transmission time (or an increase of the transmission rate) can be achieved by bonding channels of the communication system. The bonded channels typically provide a statistical multiplexing gain because the additional bandwidth is treated as a large single channel for the download. Bonding channels of the communication system can provide high speed downloading of content, such as video content, far in excess of the playback rate. Using bonded channels can relax the Quality of Service (QoS) requirements of a data stream, such as a video stream, over an internet protocol (IP) network.

Abstract: There is disclosed a technique in which any peaks above a threshold level are reduced, but not clipped, such that the effects of such peaks is reduced. Although the implementation of the technique preferably includes a clipping step, it is performed on the front-end rather than as the last step in the technique, such that the output signal is not a clipped signal. Any noise introduced by the clipping step, so-called clipping noise, is preferably filtered out of the useful frequency band of the signal.

Abstract: A method and apparatus are provided for establishing communication between entities in a communication system. The time required to establish network connectivity for CPE devices can be reduced by prioritizing and/or reducing contention between the CPE devices. The CPE devices can be divided into acquisition groups and assigned specific upstream channels on which to range. The CPE devices can randomly or pseudo-randomly range on upstream channels.

Abstract: A reduced emission transmitter may comprise an encoder partitioned into at least a group of odd encoder processing cells and a group of even encoder processing cells. A DAC may be partitioned into at least: a group of odd DAC processing cells for processing outputs of the group of odd encoder processing cells, and a group of even DAC processing cells for processing outputs of the group of even encoder processing cells. The reduced emission transmitter may further comprise an aggregator that aggregates the outputs of the odd DAC processing cells and the outputs of the even DAC processing cells to generate a reduced emissions analog DAC output. At least one clock generator is provided, which generates a first clock signal and a second clock signals that clocks the even encoder processing cells, and the odd encoder processing cells respectively. The second clock signal is a delayed version of the first clock signal.

Abstract: A method and apparatus for providing multiple clock signals for a communication device, with the clock signals being generated to correspond to the operating mode of various core modules of the communication device. A clock generator is operable to generate a plurality of clock signals having performance characteristics corresponding to the operating mode of individual cores in the system. A clock management logic circuit is operable to receive a plurality of request signals from the core modules and to cause the clock generator to generate appropriate clock signals based on the requests and other information relating to the operating mode of the core modules.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The system may use anti-aliased text and graphics to provide high quality display of graphical elements, or glyphs, which represent an image of a character of text or graphics, on television and other displays. The graphical elements may be superimposed over live video or arbitrary graphics imagery.

Abstract: An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the summed signal and outputs a quantized output signal. A limiter receives the summed signal and outputs a limited summed signal. The limiter limits the limited summed signal to ?*(maximum value of input signal), ?>1. A second summer receives the limited summed signal and the output signal and outputs an error signal. A filter receives the error signal and outputting the feedback signal. Typically, 1.0<?<2.0, more preferably 1.4<?<1.6. The filter has a transfer function of H1(z)=2z?1?z?2.

Abstract: Systems and methods that control prefetching are provided. In one embodiment, a system may include, for example, a prefetch buffer system coupled to a processing unit and to a memory. The prefetch buffer system may include, for example, a prefetch controller that is adapted to be programmable such that prefetch control features can be selected.

Abstract: A wide input range amplifier includes a first and second stage. The first stage has first and second inputs, first and second outputs, and first, second and third voltage sources. The first stage accepts input signals having a first common mode voltage range and outputs a first output signal having a second common mode voltage range and being amplified a first amount. The second stage has first and second inputs connected to the first and second outputs of the first stage, respectively. The second stage accepts input signals having a common mode voltage in the second range and outputs a second output signal having a third common mode voltage range and being amplified a second amount.

Abstract: Systems and methods for creating a limited duration clock divider reset are disclosed. Aspects of the invention may include a method for resetting a chip or a circuit. The method may include buffering a main reset input signal, inverting the main reset input signal to create an active high reset signal, resetting a counter utilizing the active high reset signal, comparing a counter output value and a counter-associated value in a comparator to obtain a comparator output value, and applying an OR logical operation to the comparator output. A limited duration clock divider reset may be generated from the output of the OR logical operation. The OR logical operation may be applied to the buffered main reset input signal. The comparator output may be inverted.

Abstract: A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a MOSFET and applying this replicated voltage to the body terminal. In this manner, the effect of the body transconductance, at high frequencies, becomes a function of the ratio of the well-to-substrate capacitance of the MOSFET to the sum of the well-to-substrate capacitance and the source-to-body capacitance of the transistor. At high frequencies, the biasing scheme mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET by contributing a negative half plane zero to the transfer function of the feedback network, and reduces the power consumed by the gain boosting amplifier.

Abstract: A circuit for clamping a TV signal includes an input capacitor coupled to the TV signal, an analog-to-digital converter that outputs a digital signal corresponding to TV signal, a comparator that compares the digital signal to a black level signal, and a high impedance driver that charges the input capacitor in response to an output of the comparator.

Abstract: A distributed arbitration scheme includes arbiters with each agent. The arbiters receive request signals indicating which agents are arbitrating for the bus. Additionally, the agent currently using the bus broadcasts an agent identifier assigned to that agent. The arbiters receive the agent identifier and use the agent identifier as an indication of the winner of the preceding arbitration. Accordingly, the arbiters determine if the corresponding agent wins the arbitration, but may not attempt to calculate which other agent wins the arbitration. In one embodiment, the arbiter maintains a priority state indicative of which of the other agents are higher priority than the corresponding agent and which of the other agents are lower priority. In one implementation, the bus may be a split transaction bus and thus each requesting agent may include an address arbiter and each responding agent may include a data arbiter.

Abstract: A printed circuit board includes two differential signal traces, a layer of core material, a layer of filler material, and a ground plane. The filler material is replaced by an air core under the differential signal traces.

Abstract: Methods and systems for reducing effects of digital loop dead zones add phase randomness to one or more asynchronous signals that are to be synchronized with a digital loop system clock. Phase randomness is added in one or more of a variety of ways including, without limitation, non-harmonic asynchronous signals and variable phase delay. The invention can be implemented in a variety of types of digital loops including, without limitation, phase locked loops (“PLLs”). For example, a PLL receives a system clock signal, a digital reference signal, and a feedback signal. The digital reference signal and/or the feedback signal is asynchronous with the system clock signal. A phase of the asynchronous signal(s) is randomized and then synchronized with the system clock signal, prior to phase difference detection. This reduces effects of digital loop dead zones that are otherwise introduced by synchronization.