Abstract: Methods and systems for reducing effects of digital loop dead zones add phase randomness to one or more asynchronous signals that are to be synchronized with a digital loop system clock. Phase randomness is added in one or more of a variety of ways including, without limitation, non-harmonic asynchronous signals and variable phase delay. The invention can be implemented in a variety of types of digital loops including, without limitation, phase locked loops (“PLLs”). For example, a PLL receives a system clock signal, a digital reference signal, and a feedback signal. The digital reference signal and/or the feedback signal is asynchronous with the system clock signal. A phase of the asynchronous signal(s) is randomized and then synchronized with the system clock signal, prior to phase difference detection. This reduces effects of digital loop dead zones that are otherwise introduced by synchronization.

Abstract: An improved high-fanin multiplexer that is highly-scalable, fast and area-efficient. In one embodiment of the present invention, multiple logic “legs” are attached to a common output line. Each leg comprises one pMOS pull-up transistor and one nMOS pull-down transistor. The gate of the pMOS transistor in each leg is connected to the output of an And-Or-Invert (AOI) gate whose inputs are connected to a plurality of select lines and a plurality of data lines. The gate of the nMOS transistor in each leg is connected to the output of an Or-And-Invert (OAI) gate whose inputs are connected to a plurality of select lines (the logical complements of the select lines for the AOI), and a plurality of data input lines. The high-fanin multiplexer of the present invention offers numerous advantages over the prior art. In particular, the high-fanin multiplexer of the present invention has very small self-loading allowing a large number of inputs while also maintaining a high fan out speed.

Abstract: A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of an I/O bus interface for a system-on-a-chip processor. In the method and apparatus of the present invention both intra-virtual channel dependencies and inter-virtual channel dependencies are fully programmable, thereby offering significant advantages over prior art I/O interfaces. The method and apparatus of the present invention is broadly comprised of a system for managing data transactions between a first bus and a second bus. A first transaction conversion module is operably connected to the first bus and is operable to receive transactions from the first bus and a first format and to convert those transactions into an internal format.

Abstract: Provided are a method and system for processing at least two consecutive MPEG Q-blocks in a communications system, one of the Q-blocks being low rate and the other being high rate. The method includes back-filling an empty portion in a first transmitted Q-block with a first portion of second type data, the remaining portion of data of the second type data being included in another Q-block prior to transmission. The second type data crosses a boundary between the first and the other Q-block when the actual number is less than a corresponding maximum number. Finally, the method includes receiving within an associated subscriber modem one of the first and the second type data and not receiving the other of the first and the second type data when the second type data crosses the boundary.

Abstract: Provided are a method and system for determining system time in a satellite based cable data communication system. The system includes a satellite modem termination system configured to transmit data frames to a receiver in a predetermined symbol rate. Each frame includes a corresponding number of symbols and has a time stamp (i) indicative of the frame's time of transmission and (ii) positioned within the frame at a location common to all of the frames. The method includes receiving at least two consecutively transmitted data frames within the receiver and registering the time stamp of the first received data frame within the receiver to produce a first time stamp. Also, the time stamp of the second received data frame is registered within the receiver to produce a second time stamp. The time of transmission of the second transmitted data frame is updated, wherein the updating is a function of the first time stamp, the second time stamp, the corresponding number of symbols, and the symbol rate.

Abstract: A method of enhancing network transmission between stations on a priority-enabled frame-based communications network, the communications network having multiple transmit priorities and transmitting frames such that a network access time to transmit a frame of a lower transmit priority is longer than a network access time to transmit a frame of a higher transmit priority, the number of transmit priorities being fixed and all stations being capable of transmitting frames at any transmit priority. The method applies to each station. An initial transmit priority is established for each frame to be transmitted. A set of initial transmit priorities assigned to frames transmitted on the communications network is maintained.

Abstract: A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is interpolated by N and processed by a digital filter to obtain the pulse shape required by the particular communication application. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. When implemented in such manner, the logical implementation and memory replaces digital filtering circuits, DAC decoding logic circuit and re-synchronization logic circuits that are conventionally implemented in hardware. Thus, the hardware functionality of these circuits is rendered into arithmetic form and implemented in a memory device.

Abstract: A system and technique for detecting a device that requires power is implemented with a power detection station. The power detection system includes a detector having an output and a return which are coupled together by the device when the device requires power. The detector includes a word generator for generating test pulses for transmission to the device via the detector output, and a comparator for comparing the detector output with the detector return. The power detection station has a wide variety of applications, including by way of example, a switch or hub.

Abstract: A numerically controlled oscillator (NCO) system for generating rational frequencies with normalized phase is disclosed. In one embodiment, the system comprises a rational NCO and a simple NCO. The rational NCO generates an overflow or correction value, based on a desired rational frequency of the system, and the simple NCO uses the overflow or correction value to generate the desired rational frequency.

Abstract: In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock.

Abstract: Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.

Abstract: A one-time programming memory element, capable of being manufactured in a 0.13 ?m or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write switch, having first and second switches coupled to the capacitor, and a read switch also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write switch to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

Abstract: A dual conversion receiver selects and down-converts one channel from a plurality of channels in a received RF signal. The dual conversion receiver includes first and second mixer stages that are driven by first and second local oscillator signals. Channel selection is performed by tuning the first local oscillator signal so that a desired channel is up-converted to a first IF frequency, which defines the center of the passband of a first bandpass filter connected between the first and second mixer stages. The second mixer stage down-converts the output of the first bandpass filter to a second IF frequency, which is further filtered by a second bandpass filter. The first and second local oscillators can produce harmonics that mix in the second mixer stage, causing unwanted spurious signals that can fall in band with the second IF frequency.

Abstract: A method and system for simulation of an electronic circuit is provided, the circuit being represented by a network of a plurality of logic elements, the circuit comprising first and second asynchronous clock domains, whereby jitter elements are additionally inserted at predetermined portions of circuit boundaries between the first and second clock domains, the jitter elements being represented as logic elements, the values of which are randomly set.

Abstract: A balancing/unbalancing (balun) structure includes two input ports are coupled to a differential signal. An isolated port is connected to ground through a matched resistance. An output port is coupled to a single-ended signal corresponding to the differential signal. A plurality of traces connect the two input ports, the load connection port and a tap point to the output port. A f2 rejection filter is wrapped around the balun and includes a first folded element with a transmission length of ?2/4 and connected to the output port. A second folded element has a transmission length of ?2/4 and connected to the tap point. A third folded element connects the tap point to the output port and has a transmission length of ?2/4.

Abstract: A protection circuit for extending the dynamic range of an amplifier circuit is described. Off-chip impedances, such as inductors, cause the output of the circuit to swing above and below the bias voltage. A protection circuit is included, either on-chip or off-chip, to protect the integrated circuit components if there is a fault condition in either of the off-chip impedances.

Abstract: A method and circuit for initializing a buffer in a clock forwarded system. A buffer is configured for temporarily storing incoming data received on the clock-forwarded interface. The buffer may use a write pointer and a read pointer which may be clocked by two different clocks allowing independent write and read accesses to the buffer. In an initialization mode, a predetermined pattern of data may be written into an entry in the buffer. In one embodiment, a logic circuit may detect the predetermined pattern of data and may cause the value of the write pointer to be captured. A synchronizing circuit may synchronize an indication that the predetermined pattern of data has been detected to the clock used by the read pointer. The synchronizer circuit may then provide a initialize signal to the read pointer which stores the captured write pointer value into the read pointer.

Abstract: A method for load balancing in a link aggregation environment, wherein the method includes the steps of determining if a packet flow in a network switch exceeds a predetermined threshold. Then the method includes the step of determining if the packet flow is a candidate for link switching from a first link to a second link if the packet flow exceeds the predetermined threshold. Additionally, the method includes switching the packet flow from the first link to the second link if the packet flow is determined to be a candidate for link switching. Additionally, a method for load balancing in a link aggregation environment including the steps of determining a length of a first frame and a length of a second frame entering the link aggregation environment. Thereafter, determining a flow rate of the first frame and the second frame entering the link aggregation environment.

Abstract: The present invention is a metal bond pad that provides electrical and mechanical connection to an integrated circuit (IC). The metal bond pad is configured to accommodate for probe travel during probing measurements, without modifying the size of the passivation opening of the bond pad. This enables higher density of active devices on the IC and therefore increases integration and lowers IC cost. The metal bond pad for the integrated circuit includes a substrate, a first metal layer, and a second metal layer. The substrate has the first metal layer disposed therein, having an opening from the top surface of the substrate. The second metal layer has a first-end portion, a second-end portion and a center portion disposed between the first-end portion and the second-end portion. The center portion of the second metal layer is aligned with the opening in the substrate and a bottom surface of the center portion is in contact with the top surface of the first metal layer.

Abstract: A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a plurality of power sources and a bias current portion having a plurality of bias current devices. The system also includes an amplification portion having a plurality of amplifiers. A first group of the plurality of amplifiers is coupled to the power source portion and the bias current portion, such that feedback voltage is substantially eliminated to substantially eliminate oscillations in the amplification portion.