Abstract: A signal recovery system and methods to quickly acquire signal lock and maintain consistent performance of the signal recovery system for different signal input rates of an input signal are provided. The system includes a phase locked loop system and a parameter controller. The method includes monitoring an input signal, determining a signal input rate of the input signal, providing shift factors to a loop filter contained within the signal recovery system, and adjusting the phase locked loop system performance based on the shift factors. The performance factors that can be modified include the acquisition rate, loop bandwidth, and damping factor of the phase locked loop system within the signal recovery system.

Abstract: An improved method and system for optimum placement of multiple antenna elements on circuit boards for wireless communication systems used in portable devices such as laptop computers and personal digital assistants (PDAs). Multiple antenna elements are placed on a circuit board with the individual antenna elements being placed such that they are orthogonal with respect to each other. In one embodiment of the present invention two antenna elements are placed on a circuit board in an orthogonal orientation to maximize the signal strength for an RF signal at a single frequency. In an alternate embodiment of the invention, four antenna elements are placed on the circuit board to maximize the signal strength for RF signals at two different frequencies. In the various embodiments of the present invention the gain characteristics of the various antenna elements are enhanced by placing the individual antenna elements in a predetermined orientation with respect to a ground plane on the circuit board.

Abstract: A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.

Abstract: A collaboration scheme for wireless communications devices implemented on a single CMOS integrated circuit is described. By providing a dynamically updateable, multiple-priority protocol, more differentiation between traffic types is provided and response time (latency) is reduced by adjusting the priority allocations between the devices when an application on one device requires greater throughput.

Abstract: A scheme for sharing antenna control pins in a wireless communications device implemented on a single CMOS integrated circuit is described. By providing a routing circuit for coupling the antenna control signal to the appropriate transceiver circuitry in a multi-transceiver system, antenna control signals may be efficiently processed using a minimum of pins on the wireless communication device.

Abstract: An improved directional coupler that significantly reduces the signal degradation problems associated with distortion caused by circuit elements used to measure the transmitted power. In a selected embodiment, the directional coupler of the present invention comprises a plurality of active elements, such as capacitors, that have values selected to ensure that the distortion created by circuit elements used to measure forward transmitted power. In an embodiment of the invention, capacitors have values selected to minimize in-band distortion signals at the fundamental carrier frequency of the transmitted signal and also at the second and third harmonics of the fundamental carrier frequency.

Abstract: A power management scheme for a wireless communications device substantially implemented on a single CMOS integrated circuit is described. The present invention provides a method and apparatus for generating first and second clock signals for a wireless communication device, with the first and second clock signals corresponding first and second power levels, depending on the operating mode of the wireless communication unit. In the first operating state, the transceiver in the RF analog module is operational and the clock generator provides a first clock signal having the high-speed, high-accuracy characteristics necessary to maintain efficient operation of the transceiver. In a second operating state, the transceiver in the RF analog module is turned off. In this second operational state, the clock generator provides a second clock signal having a frequency and quality sufficient to maintain efficient operation of the digital modules in the wireless communication device.

Abstract: A Viterbi decoding demapping scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By using log and antilog techniques, simplified multiplication and division operations in the branch metric calculation may be performed. A fully integrated receiver circuit with Viterbi decoder with branch metric computation consumes less circuit space and power than conventional solutions.

Abstract: The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a multi-bit DAC. The digital sigma-delta modulator receives a digital input signal and produces a quantized digital signal therefrom. The decimation filter receives the quantized digital signal and produces a decimated digital signal therefrom. The multi-bit DAC receives the decimated digital signal and produces an analog output signal therefrom. The analog output signal is representative of the digital input signal.

Abstract: A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e.g., wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.

Abstract: A first dynamic logic circuit has an output node on which a scan value is provided during scan, a second dynamic logic circuit, and one or more third dynamic logic circuits. The first dynamic logic circuit and the second dynamic logic circuit are in a first dynamic phase during functional operation. The third dynamic logic circuits are in a second dynamic phase during functional operation, and an output of the third dynamic circuits is sampled in response to the scan value during scan. In one embodiment, a first clock controls evaluation of the second dynamic logic circuit, and the second clock controls evaluation of the third dynamic logic circuits. The clocks may be generated responsive to a scan clock and/or a scan mode signal to generate at least one evaluate pulse on the first clock and the second clock prior to sampling the output of the third dynamic circuits.

Abstract: A method of forwarding data in a network switch fabric is disclosed. An incoming data packet is received at a first port of the fabric and a first packet portion, less than a full packet length, is read to determine particular packet information, the particular packet information including a source address and a destination address. An egress port bitmap is determined based on a lookup in a forwarding table and it is determined if the destination address belongs to a trunk group of trunked ports. The incoming data packet is forwarded based on the egress port bitmap, when the destination address does not belong to the trunk group. When the destination address does belong to the trunk group, a particular trunked port of the trunk group is determined and the incoming data packet is forwarded thereto.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Abstract: A constant impedance filter maintains a constant input impedance for frequencies that are both inside the filter passband and outside the filter passband. The constant input impedance appears as a pure resistance. The constant impedance filter includes a plurality of filter poles that are connected in series. Each of the filter poles include an inductor, a capacitor, and a resistor. The value of the inductor, the capacitor, and the resistor are selected to provide a constant input impedance over frequency for each pole of the filter, which produces a constant input impedance for the entire filter over frequency. The constant impedance filter can be implemented as a low pass filter, a high pass filter, or a bandpass filter. Furthermore, the constant impedance filter can be implemented in a single-ended configuration or a differential configuration.

Abstract: A method and system, compatible with low-voltage CMOS technology, for controlling the charging of a battery. The method includes monitoring a battery voltage with respect to a threshold voltage. The method further includes coupling a charging control logic supply to ground, generating an active low first control signal, inverting the active low first control signal, and charging the battery at a first rate when the battery voltage is below the threshold voltage. The method further includes coupling the charging control logic supply to the battery voltage, generating an active high second control signal, and charging the battery at a second rate when the battery voltage exceeds the threshold voltage. The first charging rate is slower than the second charging rate. The method further includes supplying battery power to a charger line when the battery voltage exceeds the charger voltage, and suppressing a leakage current.

Abstract: A multi-stage amplifier assembly configured to receive a terrestrial digital television (“DTV”) input signal including multiple frequency channels. The amplifier assembly optionally includes a PIN diode coupled across differential inputs to a first stage of the multi-stage amplifier assembly. The PIN diode is controlled to attenuate the input when an exceptionally large signal is present in a channel adjacent to a desired channel. The PIN diode, essentially a variable resistor, permits the multi-stage amplifier assembly to maintain dynamic range in such situations for reasonable tradeoffs. The amplifier assembly further optionally includes an out-of-band second stage LNA. The amplifier assembly further optionally includes a mutli-band input filter. The multi-band filer insures that the AGC operates on the TV band of interest, thus improving the linearity of the system. The invention can be implemented in CMOS and/or SiGe.

Abstract: A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.

Abstract: A system includes a support device and an elongated spiral antenna coupled to the support device. The elongated spiral antenna has a contracted portion and an expanded portion. The expanded portion provides beam steering and directivity. The system also includes a feed line coupled to the elongated spiral antenna. A method for forming the elongated spiral antenna uses a predetermined formula to form arms of the elongated spiral antenna. The arms can be formed by printing the arms on a printed circuit board.

Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier. One embodiment of the present invention relates to a memory device comprising a plurality of synchronous controlled global elements and a plurality of self-timed local elements. In this embodiment, at least one of the self-timed local elements interfaces with the synchronous controlled global element.

Abstract: Vector orthogonal frequency division multiplexing (VOFDM) receiver correlation matrix processing using factorization. Efficient correlation matrix processing is used to combine multiple signals into a single combined signal. This single combined signal may be viewed as being a beam form soft decision. An efficient square root factorization system and method provides for computational resource savings while, at the same time, providing for greater precision of the overall computational results. By reducing intermediate variable calculation dynamic ranges, the overall calculation becomes more precise. Particularly within fixed-point arithmetic applications, a reduction in dynamic range of the intermediate variable calculations provides for a significant increase in final calculation precision.