Abstract: A scaled input current is produced that substantially matches the full scale input of a CT??ADC that substantially cancels an offset bias current component of the input current. A variable bias resistance value is coupled between the integrator input and one of a supply voltage and a circuit common. The method further includes integrating the input current to produce an integrated signal representing a time averaged value of the input current to substantially remove noise from a frequency band of interest. The integrated signal is produced to a quantizer to produce a feedback current that substantially cancels a quantization noise component in the digital representation of the scaled analog signal by coupling the digital representation of the scaled analog signal to a programmable digital switch wherein the programmable digital switch either sinks current from or sources current to the integrator input.

Abstract: An integrated Ethernet PHY/MAC apparatus having a single link partner capability register shared between a PHY and a corresponding MAC, which implements IEEE Standard 302.3, including IEEE Standards 802.3u and 802.3x. Apparatus also includes plural PHYs, each having a corresponding MAC integrably coupled therewith such that an integrated multi-port Ethernet device is realized. A network consists of at least one integrated Ethernet PHY/MAC device having a single link partner capability register.

Abstract: A video and graphics system includes a data transport processor for receiving compressed data streams, a video transport processor for extracting video data, and an audio decode processor for extracting audio data. The data transport processor provides PCRs to the video transport processor and the audio decode processor. The video transport-processor stores the video data in external memory and generates a start code table to index the video data stored the external memory. In the start code table SLICEs of the video data are aligned to a suitable boundary. The compressed data streams may include MPEG Transport streams, and the video data may include SDTV or HDTV data. The video and graphics system may be implemented on an integrated circuit chip.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A memory management system provides the ability for multiple requesters to access blocks of memory in a pipelined manner. During a first clock, requests for one or more of the memory blocks are received by the system. A determination is made of whether one of the memory blocks is requested by one or more requests. If the same memory block is requested by two or more requests, the system performs a further determination of which of the requests will be provided to the memory block. The determined request is provided to the memory block on the first clock. During a second clock, the data of the determined request is latched to the memory block and a memory access is initiated. If the request is a write request, the data is written to the memory block. If the request is a read request, then the requested data is retrieved and, on a third clock, the data is driven onto a bus, routed to the determined requester, and available to be latched into the requester on the fourth clock.

Abstract: The present invention relates to a design of a computer system that processes instructions with a specific operation code causing the processor to execute a certain operation twice and a method for running such computer system in a time and register space saving manner. A method is provided for executing at least one computer instruction which defines at least a first source operand and an operation to be carried out on the operand, the instruction containing at least one address field of a predetermined bit length and at least one repeated execution bit related to the first operand. The method includes accessing the first source operand; accessing the repeated execution bit and deriving from that repeated execution bit a repeated execution code defining a repeated execution condition; and selectively carrying out the operation defined in the instruction once, twice or more times in dependence of the repeated execution code.

Abstract: The invention refers to a computer system, comprising: a computer, and a peripheral device, wherein the computer comprises one or more receivers for receiving signals sent from the peripheral device, and a peripheral device movement detector for detecting a movement of the peripheral device from the signals received from the peripheral device. Further, the invention referes to a mobile telephone, comprising a device movement tracking member, e.g., a rollerball. In addition, the invention refers to a computer system, comprising: a mobile telephone comprising a device movement tracking member, and a computer connectable to the mobile telephone, e.g. via a wireless RF connection.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: A system and method for an improved analog front-end system is disclosed. By coupling a switch to the output of a track-and-hold circuit and to the input of a time-discrete circuit, such as an analog-to-digital converter, the time-discrete circuit can be disconnected from the track-and-hold circuit during the track mode of the track-and-hold circuit. This improved system reduces the load of the T/H circuit from the full input capacitance of the time-discrete circuit to the smaller parasitics of the switch thereby providing a T/H circuit with lower power consumption and smaller area while maintaining high speed and high accuracy.

Abstract: The invention refers to an electronic system, comprising several power-dissipating components, and a circuit board, wherein said power-dissipating components are mounted both to a top side and a bottom side of said circuit board. Further, the invention refers to method for mounting power-dissipating components onto a circuit board, comprising the steps of (a) determining the thermal behavior of said power-dissipating components; and (b) determining, in accordance thereto, the placement of said power-dissipating components on both a top side and a bottom side of said circuit board.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache. The present invention improves the of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: A system and method for optimizing the power level in the upstream direction in an ADSL communication system are disclosed. The system and method optimize the upstream signal power level by determining at least one system parameter related to the transmission of the input communications signal and modifying the bit and gain tables in response to the system parameter to optimize the upstream power level. More specifically, in one embodiment, the present invention selects a maximum received power configuration parameter for a receiving device, measures the received signal power at the receiving device, determinines a power backoff parameter for the transmitting device, uses the power backoff to modify the bit and gain tables and communicates the modified bit and gain tables to the transmitting device.

Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

Abstract: A low-noise, fast-settling bias circuit includes a first and a second low pass filter, such as RC filters. The second filter initially shorts out a resistor of the first filter with a switch (set to low impedance) in parallel. Accordingly, a capacitor of the first filter quickly charges up to the same voltage as the input bias voltage. As the second filter charges up, the switch slowly shuts off (high impedance). By this time, since the capacitor of the first filter has charged to the same voltage as the bias voltage, a large RC formed by the resistor of the first filter and the capacitor of the first filter is available to provide filtering for the desired bias current.

Abstract: An RF communications system includes a transmit node for transmitting an RF information signal and a receive node for receiving the transmitted RF information signal. The receive node includes a passive mixer coupled to an amplifier for producing an IF or baseband differential mixer output signal as a function of a LO drive signal. The passive mixer having a first plurality of transistors of a first polarity type arranged in a ring configuration and a second plurality of transistors of a second polarity type, wherein each of second plurality of transistors is coupled to one of the first plurality of transistors.

Abstract: A packet-switched multiple-access network system with a distributed fair priority queuing media access control protocol that provides multiple levels of priority of access and fair collision resolution with improved performance is disclosed. In one embodiment, the system provides high-speed transport of multimedia information on a shared channel. Further, in one embodiment, MAC level side-band signaling that is useful to other levels of the network protocol (e.g., the physical layer) is also provided.

Abstract: Continuously tuning a transconductance. Coupling a degeneration resistance from a first source of a first transistor in a differential pair of transistors to a second source of a second transistor in the differential pair of transistors. Applying a second variable degeneration resistance in parallel to the first degeneration resistance in response to the application of a first variable control voltage. And applying a third variable degeneration resistance in parallel to the first degeneration resistance and the second degeneration resistance in response to the application of a second variable control voltage having a fixed voltage offset from the first variable control voltage.

Abstract: A power amplifier includes a transconductance stage and a modulation detection and bias determination module, and may include a cascode stage. The modulation detection and bias determination module operably couples to the transconductance stage and to the cascode stage when present and is operable to detect modulation characteristics of an signal operated upon by the transconductance stage. The modulation detection and bias determination module is also operable to controllably bias the transconductance stage and/or the cascode stage when present based upon detected modulation characteristics. The detected modulation characteristics are typically determined based upon a measured signal level, e.g., voltage level, current level, or power level, of the signal operated upon by the transconductance device. For non-constant envelope modulations, the signal level varies over time with the modulation envelope. The operational characteristics of the power amplifier, e.g.

Abstract: According to the present invention, simultaneous call-handling and data transfer is achieved between a terminal and a multi-line gateway in a cordless telephony environment. Multiple logical channels are established and used as signaling resources for calls on the multiple lines, and also for data transfers between the gateway and terminal. As a result, terminals can handle multiple calls on different lines and at the same time access data stored at the gateway. According to a first aspect of the present invention, two or more logical channels are established over an asynchronous channel between a terminal and a gateway. These logical channels are assigned to calls that are set-up between the terminal and gateway. When used as a signaling resource, the logical channels allow the terminal to distinguish between signaling information for multiple simultaneous calls. The calls are associated with another speech or data channel that will bear the voice signal, referred to herein as a bearer channel.