Abstract: A content addressable memory cell (10) comprises a word line 12, a first bit line (14), and a second bit line (16). A pair of transistors (30–31) is arranged to store bits of data at first and second points (35 and 36). A first transistor (26) is coupled to the word line, the first bit line and the first point. A second transistor (27) is coupled to the word line, the second bit line and the second point. The word line voltage is changed in accordance with process parameters to allow conduction by the first and second transistors to compensate for leakage by the pair of transistors. For example, the first and second transistors may be operated in a triode mode.

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: A method and system are disclosed for efficiently and effectively toggling logic states of chip elements during a burn-in process of a digital integrated circuit chip. A set of IDDQ patterns are generated by a design simulation tool, based on the design of the chip, during a simulation of the design. The set of IDDQ patterns are translated to a set of burn-in patterns that are compatible with a pattern format of a burn-in board using a pattern translation tool. The set of burn-in patterns are stored in memory on the burn-in board and shifted into the memory during the burn-in process to aid in toggling logic states of the chip elements.

Abstract: Systems and methods for testing a circuit are provided. In one example, a sequential device for use in a scan chain is described. The sequential device may include a scan input, a scan output and a functional data output. The functional data output may be coupled to the scan input and to the scan output. The functional data output may be coupled to the scan output via a delay buffer.

Abstract: A design of integrated circuit components to prevent accidental turn on when large input signals are accepted. With integrated circuits operated at lower power supply voltages, input signals having large peak values can tend to turn on devices within the integrated circuit erroneously. By placing amplifiers within the integrated circuits where input signals are received and removing the power of such amplifiers, accidental turn on can be minimized.

Abstract: A system and method for high-quality variable speed playback of audio-visual (A/V) media is provided. The system receives an encoded visual signal and an encoded audio signal. The encoded visual signal is decoded to generate a decoded visual signal and the encoded audio signal is decoded to generate a decoded audio signal. The decoded audio signal is time scale modified to generate a time scale modified audio signal. The decoded visual signal and the time scale modified audio signal are then synchronized for playback at a predefined playback speed. Only partial decoding of the encoded audio signal may be performed to conserve processing power.

Abstract: A method and system of executing computer instructions is described. Each instruction defines first and second operands and an operation to be carried out on said operands. Each instruction also contains an address field of a predetermined bit length which identifies a test register holding a plurality of test bits greater than the predetermined bit length. The test register holds a test code defining a test condition. The test condition is checked against at least one condition code and the operation is selectively carried out in dependence on whether the condition code satisfies the test condition. In one embodiment, the condition codes are set on a lane-by-lane basis for packed operands.

Abstract: A network device including at least one network port, a clock, address resolution (ARL) tables, and address resolution logic. The at least one network port is configured to send and receive a data packet. The clock is for generating a timing signal. The ARL tables are configured to store and maintain data related to port addresses of the network device. The address resolution logic is coupled to the ARL tables and configured to perform a search and an update to data into the ARL tables based on the data packet, to calculate a current range of the search, to determine an intended result of the update, and to block the update when the intended result will move data out of the current range of the search, the search and the update being performed concurrently during alternating slots of the timing signal.

Abstract: A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a headend and a plurality of cable modems located different distances from the headend. The power transmission level, slot timing, and equalization of the cable modems are set by a ranging process. Data is transmitted by the modems in fragmented form. Various measures are taken to make transmission from the cable modems robust. The upstream data transmission is controlled to permit multiple access from the cable modems.

Abstract: A system and method are disclosed that provide for compatibility between different generations of transceivers, such as Gigabit Ethernet transceivers. According to the invention, a novel transceiver is provided that includes a physical layer entity (PHY) comprising a physical coding sublayer (PCS) and a physical medium attachment (PMA) sublayer. In one embodiment, the PHY is designed to switch the PCS encoding/decoding scheme to a legacy-based encoding/decoding scheme in a situation where it is determined that the remote transceiver in communication with the novel transceiver is transmitting data according to a legacy-based scheme.

Abstract: A node is coupled to receive a coherency command and coupled to a memory, wherein the node includes a directory configured to track a state of a first number of coherency blocks less than a total number of the coherency blocks in the memory. The directory is configured to allocate a first entry to track the state of the first coherency block responsive to the coherency command. If the first entry is currently tracking the state of a second coherency block, the second node is configured to generate one or more coherency commands to invalidate the second coherency block in a plurality of nodes.

Abstract: The benefits of on-chip self testing are widely recognized and include the capability to test at high operating speed and independently of external test equipment timing and accuracy limitations. However caches present difficulties since for testing purposes they are conventionally regarded as separate RAM and CAM arrays. The disclosed test engine tests the cache as a whole (i.e., RAM, CAM and comparators together). In the test mode, cache writes are absolutely addressable, selecting a particular entry in a particular way-set during each operation using line addressing and common tag data. This enables read operations to access a specific cache line as if absolutely addressable based on only a partial address and the known tag setting.

Abstract: An integrated burst FSK receiver is provided to receive and interpret an RF signal using FSK modulation. The integrated burst FSK receiver uses a programmable RF local oscillator to mix a received signal down to an IF range or baseband, where it is filtered and sampled for subsequent digital processing. Digital filtering and detection are employed to improve overall bit error rate performance and receiver sensitivity. A programmable digital low-pass or band-pass filter can also be used to suppress interference. A matched filter correlator can be used for detection and symbol timing adjustment in one mode, while an adaptive frequency comparator can be used in another mode. Circuits are provided that estimate carrier offset, frequency deviation and signal strength. These measurements can then be used to optimize the receiver performance. A method for receiving and interpreting an RF signal using FSK modulation is also provided.

Abstract: A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.

Abstract: A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.

Abstract: A system and method for providing antialiasing of a graphical image on a display is disclosed. The graphical image is generated from data describing at least one object. The display includes a plurality of pixels. The at least one object includes a plurality of fragments. A portion of the plurality of fragments intersects a pixel of the plurality of pixels. Each of the plurality of fragments including an indication of a portion of a corresponding pixel that is intersected. The system and method include providing at least one active region for the pixel. The at least one active region intersects a first portion of the pixel. The method and system also include providing at least one new region. A first portion of the at least one new region indicates where in the pixel the at least one active region and the fragment intersect. A second portion of the at least one new region indicates where in the pixel the at least one active region and the fragment do not intersect.

Abstract: A cable modem system and method is provided for the transfer and processing of data in accordance with specialized data transfer protocols while utilizing conventional cable modem termination system (CMTS) equipment. A cable modem system in accordance with the invention includes a cable modem that provides for the modification of data packets in accordance with one or more proprietary protocols and the addressing of the modified data packets to a CMTS. The CMTS is adapted to reconstruct the data packets.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A periodic signal generation circuit includes a differential crystal oscillator suitable for integration on a semiconductor substrate. The oscillator utilizes an external crystal as a resonator. The circuit is designed such that differential sinusoidal signals are present on the resonator leads to provide superior noise rejection of interfering signals. Differential signal transmission is maintained throughout the oscillator to reject noise generated by other circuitry that may be present on the substrate. Noise radiated out from the oscillator through the power supply, substrate, bond wires and pads is reduced due to the generation of differential signals of controlled sinusoidal amplitude and low harmonic content. The oscillator produces low phase noise so that the oscillator may be used in applications, such as TV receivers, that are sensitive to distortion. The circuit is a square wave that has low jitter, thus reducing jitter produced in digital circuits that, would utilize this square wave clock signal.

Abstract: Analog signals encoded with quadrature amplitude modulation (QAM) pass through a coaxial cable at a particular baud rate. These signals have a carrier frequency individual to the TV station being received. They are mixed with signals from a variable frequency oscillator to produce signals at a particular intermediate frequency (IF). An analog-digital converter (ADC) converts the IF signals to corresponding digital signals which are demodulated to produce two digital signals having a quadrature phase relationship. After being filtered and derotated, the digital signals pass to a symmetrical equalizer including a feed forward equalizer (FFE) and a decision feedback equalizer (DFE) connected to the FFE in a feedback relationship. The DFE may include a slicer providing amplitude approximations of increasing sensitivity at progressive times. Additional slicers in the equalizer combine the FFE and DFE outputs to provide the output data without any of the coaxial cable noise or distortions.