Abstract: A noise feedback coding (NFC) system and method that utilizes a simple and relatively inexpensive general structural configuration, but achieves improved flexibility with respect to controlling the shape of coding noise. The NFC system and method utilizes an all-zero noise feedback filter that is configured to approximate the response of a pole-zero noise feedback filter.

Abstract: A loader module for loading program code into a memory is described, whereby the memory may be partially defective, with non-defective parts of the memory being indicated by diagnostic information. The loader module is adapted for loading program code, in accordance with the diagnostic information, into non-defective parts of the memory, and for relinking the program code in accordance with the memory locations it has been loaded to. Furthermore, a method for loading program code into a memory is described. The method comprises the following steps which may be carried out in arbitrary order: loading program code, in accordance with diagnostic information, into non-defective parts of the memory, and relinking the program code in accordance with the memory locations it has been loaded to.

Abstract: A system and a method for testing a comparator include generating two triangular waveform segments having the same period and different amplitudes, inputting the two triangular waveform segments into a comparator, receiving an output of the comparator, and calculating threshold voltages of the comparator based on the output. A periodic waveform can also be generated with repeating triangular waveform segments having the same period and different amplitudes as input to the comparator.

Abstract: A data shuffler apparatus shuffles input bits to perform dynamic element matching. The shuffler apparatus includes N input shufflers, each input shuffler having N input terminals and N output terminals, each input terminal of each input shuffler receiving a respective one of the input bits. The apparatus also includes N output shufflers, each output shuffler having N input terminals and N output terminals, the input and output shufflers being interconnected such that each of the N output terminals of each input shuffler is connected to a respective input terminal of a different one of the N output shufflers.

Abstract: A method and system for providing a graphical image on a display is disclosed. The image is provided from data describing at least one object. The display includes a plurality of pixels. Each of the plurality of pixels has a size and a plurality of display elements. Each of the plurality of display elements has a color. The data includes a plurality of fragments for the at least one object. The plurality of fragments intersects a portion of the plurality of pixels. Each of the plurality of fragments includes a texture and at least one color. The method and system include ensuring that a texture area corresponds to the size of the pixel for the plurality of fragments and taking a plurality of samples of the at least one color for each of the plurality of fragments. The plurality of samples corresponds to the plurality of display elements. The method and system also include processing the texture for each of the plurality of fragments using the texture area.

Abstract: A tool for analyzing timing violations reports is presented herein. The tool comprises a script which parses a log file containing any number of timing violation reports from a simulation of a layout design. The tool filters, consolidates, and sorts the timing violations and presents the foregoing in a report of consolidated timing violations. The report of consolidated timing violations can then be analyzed by a verification engineer.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having (n?1)-tier memory modules, which are coupled with (n)-tier sense amplifiers and (n)-tier decoders. Also provided are a single-ended sense amplifier having sample-and-hold reference, and a charge-share limited-swing-driver sense amplifier; an asynchronously-resettable decoder; a wordline decoder having row redundancy; a redundancy device having redundant memory cells operated by a redundancy controller; a diffusion replica delay circuit; a high-precision delay measurement circuit; and a data transfer bus circuit imposing a limited voltage swing on a data bus. Methods are provided for a write-after-read operation without an interposed precharge cycle, and write-after-write operation with an interposed precharge cycle are provided, either operation being completed in less than one memory access cycle.

Abstract: An on-chip inductor and/or on-chip transformer includes at least one dielectric layer and at least one conductive winding on the at least one dielectric layer. The conductive winding has a substantially square geometry and has at least its exterior corners geometrically shaped to reduce impedance of the conductive winding at a particular operating frequency. Since the quality factor of an on-chip inductor is inversely proportional to the effective series impedance of an inductor at an operating frequency, by reducing the effective series impedance, the quality factor is increased.

Abstract: A method of concealing bit errors in a signal is provided. The method comprises encoding a signal parameter according to a set of constraints placed on a signal parameter quantizer. The encoded signal parameter is decoded and compared against the set of c-onstraints. Finally, the method includes declaring the decoded signal parameter invalid when the set of constraints is violated.

Abstract: The present invention is directed to systems for evaluating one-time programmable memory cells. A threshold current is applied to a resistive circuit, thereby generating a threshold voltage. A read current is applied to a first memory cell, thereby generating a memory cell voltage. The memory cell voltage is compared to the threshold voltage, thereby determining the state of the memory cell. In a further embodiment of the invention, a second threshold voltage is generated and compared the memory cell voltage, thereby verifying the state of the memory cell. The threshold current is optionally a substantial replica of said read current. The threshold current is optionally a proportional substantial replica of said read current. In an embodiment, the resistive circuit includes a second memory cell, which can be programmed or unprogrammed. The second memory cell is optionally arranged to average the memory cell resistance.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.

Abstract: A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

Abstract: A network device for handling data and a method for handling data in a network device are disclosed. The network device includes at least one media port and at least one high speed docking station, communicating with the at least one media port. At least one master is provided in the network device, where the at least one master is connected to the at least one high speed docking station. The master is configured to handle and process data received by the at least one media port and passed to the master through the at least one high speed docking station. The network device is configured to handle media ports of different media types. Thus, the device can handle data received through different media ports that have different media types with the same master, making the network device easily configured to meet a customer's needs.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.

Abstract: A memory cell circuit for modification of a default register value in an integrated circuit chip, which includes a plurality of metal layers and first and second supply potentials. The circuit comprises a memory cell, a register and a control circuit. The memory cell has a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is coupled to one of the first and second supply potentials, a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is coupled to the other one of the first and second supply potentials, and an output, wherein a state of the output is programmable by altering any one of the plurality of metal layers or any one of a plurality of via layers. The register has a data input, a data output and control inputs. The control circuit is coupled to the control inputs of the register.

Abstract: A method and system for debugging an executing service on a pipelined CPU architecture are described. In one embodiment, a breakpoint within an executing service is set and a minimum state of the executing service is saved. In addition, a program counter of the executing service is altered. The program counter is restored and the state of the executing service is restored.

Abstract: A system and method for hardware based reassembly of a fragmented packet is shown. The method includes receiving a bandwidth request to transfer a data packet from the data provider. Then, bandwidth is allocated to the data provider, where the allocated bandwidth is less than the requested bandwidth. Next, the present invention receives part of the data packet in the allocated bandwidth from the data provider, where the part of the data packet includes a fragment header, and the fragment header includes a sequence number for the part of the data packet. The part of the data packet is then stored in external memory. Finally, the data packet is reassembled by concatenating in the correct sequence the part of the data packet with other parts of the data packets to create the reassembled data packet.

Abstract: Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.

Abstract: An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.