Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.

Abstract: There is disclosed a system for designing circuits which involves pre-placing delay elements between circuit components susceptible to shoot-through due to effects of clock skew, each delay element having a physical form and at least one input terminal and at least one output terminal; determining which delay elements are not critical in preventing shoot-through; removing non-critical delay elements from the circuit; and replacing each removed delay element with a cell having a physical form equivalent to the physical form of the removed delay element and a wire connection between an input and an output of the cell equivalent to an input and output of the delay element. This wire cell has the effect of removing the delay element from the circuit without having to reposition the circuit components. This has the result that it is not necessary to re-position circuit components on the removal of delay elements and then to re-evaluate the circuit performance. Circuit design can be significantly improved.

Abstract: In the present invention, a plurality of carriers in a multi-carrier DMT communication system is grouped into one or multiple carrier groups according to at least one carriergroup parameter. A carriergroup parameter defines a parameter relating to each carrier group rather than to individual carriers, and is used for receiving and transmitting messages or data using the carrier group or groups. In one embodiment of the present invention, multiple carrier groups of fixed-size are determined and the worst case signal-to-noise ratio for each carrier group is used for the carriergroup parameter for that specified carrier group. In another embodiment of the present invention, multiple carrier groups of variable-size are determined based on a carriergroup parameter such as a carriergroup bitloading parameter. The carriergroup bitloading parameter and the worst case carriergroup SNR parameter for each carrier group are used to define each carrier group for transmitting and receiving messages or data.

Abstract: Multi-concentric pad (MCP) arrangements provide for increased pad densities on integrated circuits. The multi-concentric pad (MCP) configuration includes a first set of input output (IO) pads and a second set of IO pads, both disposed on an integrated circuit die. Each IO pad in said first set and said second set of IO pads includes a bond pad for receiving a bond wire connection, and an IO circuit coupled to the bond pad. The IO circuits provide an interface between a signal received at the corresponding bond pad and a core circuit disposed on said IC die. The first set of IO pads are arranged closer to the perimeter of the IC die than the second set of IO pads. Furthermore, the second set of IO pads are arranged so that each IO circuit in the second set of IO pads is closer to the center of the IC die than a corresponding IO circuit in the first set of IO pads.

Abstract: The present invention relates to a system and method for providing distributed, highly configurable modular predecoding. The method comprising forming a hierarchical memory structure including forming a first portion of the hierarchical memory structure adapted to perform a first layer of address predecoding. The method further comprises forming a second portion of the hierarchical memo structure interacting with at least the first portion and adapted to perform a second layer of address predecoding.

Abstract: A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.

Abstract: A method is provided for reducing power dissipation within a communications system having a plurality of adaptive filters with a plurality of taps, each tap is switchable between an active and an inactive state, each tap also has a coefficient. An acceptable error for the system is specified. This error is typically the mean squared error of the system. A tap threshold is set for each active tap. Those taps having a coefficient with an absolute value less than the tap threshold set for the active tap are deactivated. The error of the system is computed and compared to the acceptable system error. If the computed system error is less than the acceptable system error, the tap threshold for each active tap is increased.

Abstract: In one aspect, the invention describes a mechanism for refreshing multiple memory words (rows) per refresh cycle, the number of simultaneously refreshed rows being programmable by a small number of inputs. In another aspect, the invention discloses a mechanism for refreshing all banks or a programmable number of banks simultaneously in a multi-bank memory. In yet another aspect, the present invention describes a mechanism for refreshing a programmable multiple memory rows and a programmable multiple banks simultaneously.

Abstract: A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what, if any, errors have occurred. If the real-time system, such as a transceiver in a communication system, has adaptive components, the status of the adaptive components is used to estimate the condition of any external systems coupled to the real-time system.

Abstract: A method of determining a collision between two or more transmitting stations at one of the transmitting stations on a frame-based communications network. A transmitted frame header includes a cyclic preamble wherein identical copies of a preamble symbol sequence are transmitted sequentially. A collision is declared if an estimate of error power in second and third copies of the preamble minus an estimate of error power in third and fourth copies of the preamble exceeds a first threshold, or a maximum value of the norm of each term of a source field error vector minus a greater of the estimate of the error power in the second and third copies of the cyclic preamble and the estimate of the error power in the third and fourth copies of the preamble exceeds a second threshold.

Abstract: The present invention relates to a programmable memory cell and a method of setting a state for a programmable memory cell. The memory cell includes two thin gated fuses adapted to set the state of the memory cell. A level shifter device is connected to the gated fuses and is adapted to stand off a high voltage when setting the state of the memory cell. At least one switch transistor is connected to at least the level shifter device and is adapted to select at least one of the gated fuses, enabling a high voltage to be communicated thereto, thus setting the state of the memory cell.

Abstract: A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver system, by providing strings of known symbols. The string of known symbols may be the same as the symbols within a training header that appears at the beginning of a data frame. Frame parameters may be tailored to individual users and may be controlled by information pertaining to receivers, such as bit error rate, of the receiver. Additional headers may be interspersed within the data in order to assist in receiver synchronization. Frames of data may be acquired quickly by a receiver by having a string of symbols representing the phase offset between successive header symbols in the header training sequence in order to determine the carrier offset.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: A power supply and switching technique is provided that utilizes a first battery and a second battery to charge a load. The power supply includes a first controlled power switch coupled to the first battery and the load, a second controlled power switch coupled to the second battery and the load, and a power controller coupled to the first controlled power switch, the second controlled power switch and the load. The power controller monitors the voltage and the load and causes a charge to be applied to the load when the load voltage is not a predetermined voltage. The power controller causes a charge to be applied to the load by selectively closing the first controlled power switch, thereby providing a charge from the first battery to the load, and/or selectively closing the second controlled power switch, thereby providing a charge from the second battery to the load. A similar switching technique may be used to recharge the first and second battery by alternately coupling them to an external power source.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: The present invention describes a communications system having a first link partner and a second link partner that are connected by a communications link having at least four pairs of conductors. According to IEEE Standard 802.3 (e.g. Ethernet) for 1000Base-T, a data link is maintained (in a period absent data transmission) by sending idle signals over four pairs of conductors of the cable to maintain a logical connection. This idle signal scheme is replaced with an alternate idle signaling scheme that uses only two pairs of conductors to maintain a logical connection and therefore can operate with using lower power. The other two pairs of conductors of the four pairs of conductors are unused to maintain a logical connection absent data transfer, and therefore can be used to implement a Suspend Mode of operation. During Suspend Mode, the physical layer of each link partner powers down unnecessary circuitry so as to operate in a low power environment.

Abstract: A differential line driver includes a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von). Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin. A source of the first PMOS transistor is connected to a source of the second PMOS transistor. A source of the first NMOS transistor is connected to a source of the second NMOS transistor. First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von. Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop.

Abstract: A K-bit information signal represented by a polynomial U(x) having a degree K?1 is received. The information signal is transformed to form a transformed information signal using a first transform represented by a polynomial G1(x) having a degree P. The transformed information signal is represented by a polynomial T(x) having a degree K+P?1. T(x) equals U(x)G1(x). An initial cyclic code represented by a polynomial R1(x) is generated for the transformed information signal using a second transform represented by a polynomial G2(x), where G2(x) has high-order leading-zero terms. R1(x) equals the remainder obtained by dividing T(x) by G2(x). The initial cyclic code is transformed to form a final cyclic code represented by a polynomial R2(x) using the first transform. R2(x) equals R1(x)/G1(x).

Abstract: An integrated circuit formed on a semiconductor chip, comprising a low pass filter circuit having a first resistor of a first resistance value and a capacitor of a first capacitance value, wherein the first resistance value and the first capacitance value determine a corner frequency of the filter; and a tuning circuit having a second resistor of a second resistance value, a switched-capacitor of a third resistance value and a comparator that compares two voltage signals to produce a control signal, wherein the control signal adjusts the first and second resistance values as a function of the third resistance value. The corner frequency of the filter can be adjusted by varying one or more reference voltage signals. In combination, the corner frequency of the filter is adjusted by changing the frequency of a clock that controls the switched-capacitor to decrease the circuit sensitivity.